PDF: 09005aef82d283a8/Source: 09005aef82d28271 Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTS72C1Gx72.fm - Rev. A 8/07 EN
6 ©2007 Micron Technology, Inc. All rights reserved.
8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM
General Description
General Description
The MT72HT(Z)S1G72P DDR2 SDRAM module is a high-speed, CMOS, dynamic
random access 8GB memory module organized in a x72 configuration. This DDR2
SDRAM module uses internally configured, 8-bank, 2Gb TwinDie™ DDR2 SDRAM
devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Register and PLL Operations
DDR2 SDRAM modules operate in registered mode, where the command/address input
signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM
devices on the following rising clock edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and redrives the differential clock signals
(CK, CK#) to the DDR2 SDRAM devices. The register(s) and PLL reduce address,
command, control, and clock signal loading by isolating the memory devices from the
system controller. PLL clock timing is defined by JEDEC specifications and ensured by
use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL.
Parity Option
If provided from the system memory controller, (P
AR_IN) is compared within the register
to the command and address inputs of the register. An even number of ones among
these inputs is defined as valid parity. In the case that invalid parity is detected, E
RR_OUT
will be set LOW.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
2
C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to V
SS on the
module, permanently disabling hardware write protect.
