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HTS72C1Gx72.fm - Rev. A 8/07 EN
8 ©2007 Micron Technology, Inc. All rights reserved.
8GB (x72, ECC, QR) 240-Pin DDR2 SDRAM RDIMM
Electrical Specifications
IDD Specifications
Table 8: DDR2 IDD Specifications and Conditions – 8GB
Values are shown for the MT47H512M4THN DDR2 SDRAM only and are computed from values specified in
the MT47H256M4 2Gb TwinDie™ component data sheet
Parameter/Condition Symbol -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are switching; Data bus inputs are switching
ICDD0 2,592 2,322 2,232 mA
Operating one bank active-read-precharge current: I
OUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RAS =
t
RAS MIN (IDD),
t
RCD =
t
RCD (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data pattern is same as
I
DD4W
I
CDD1 2,862 2,772 2,592 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
ICDD2P 594 594 594 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
I
CDD2Q 1,782 1,782 1,602 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
ICDD2N 1,782 1,782 1,602 mA
Active power-down current: All device banks open;
t
CK =
t
CK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
ICDD3P 1,008 1,008 1,008 mA
Slow PDN exit
MR[12] = 1
648 648 648 mA
Active standby current: All device banks open;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Other control and address bus inputs are switching; Data
bus inputs are switching
I
CDD3N 2,052 1,872 1,692 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
CDD4W 3,222 3,042 2,592 mA
Operating burst read current: All device banks open; Continuous burst
reads; I
OUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
t
CK =
t
CK (IDD),
t
RAS =
t
RAS MAX (IDD),
t
RP =
t
RP (IDD); CKE is HIGH, S# is HIGH between
valid commands; Address bus inputs are switching; Data bus inputs are
switching
I
CDD4R 3,222 3,042 2,592 mA
Burst refresh current:
t
CK =
t
CK (IDD); REFRESH command at every
t
RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other
control and address bus inputs are switching; Data bus inputs are switching
ICDD5 4,932 4,842 4,662 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I
CDD6 594 594 594 mA
Operating bank interleave read current: All device banks interleaving
reads; I
OUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 ×
t
CK (IDD);
t
CK =
t
CK (IDD),
t
RC =
t
RC (IDD),
t
RRD =
t
RRD (IDD),
t
RCD =
t
RCD (IDD); CKE is
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
I
CDD7 6,102 5,922 5,652 mA
