X40015S8I-A Datasheet X40010S8-A, X40010V8-AT1, X40011V8-C | P7-P9

FN8111.0

March 28, 2005

PUP1, PUP0: Power Up Bits (Nonvolatile)

The Power Up bits, PUP1 and PUP0, determine the

PURST

time delay. The nominal power up times are

shown in the following table.

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the

Watchdog Timer. The options are shown below.

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and

trickle registers requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation pre-

ceded by a start and ended with a stop).

– Write a 06H to the Control Register to set the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation proceeded by a start

and ended with a stop).

– Write a one byte value to the Control Register that

has all the control bits set to the desired state. The

Control register can be represented as qxys 001r in

binary, where xy are the WD bits, s isthe BP bit and

qr are the power up bits. This operation proceeded

by a start and ended with a stop bit. Since this is a

nonvolatile write cycle it will take up to 10ms to

complete. The RWEL bit is reset by this cycle and

the sequence must be repeated to change the non-

volatile bits again. If bit 2 is set to ‘1’ in this third step

(qxys 011r) then the RWEL bit is set, but the WD1,

WD0, PUP1, PUP0, and BP bits remain unchanged.

Writing a second byte to the control register is not

allowed. Doing so aborts the write operation and

returns a NACK.

– A read operation occurring between any of the

previous operations will not interrupt the register

write operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write

protected block.

To illustrate, a sequence of writes to the device con-

sisting of [02H, 06H, 02H] will reset all of the nonvola-

tile bits in the Control Register to 0. A sequence of

[02H, 06H, 06H] will leave the nonvolatile bits

unchanged and the RWEL bit remains set.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user

the status of what causes the system reset active. The

Manual Reset Fail, Watchdog Timer Fail and three

Low Voltage Fail bits are volatile.

The FDR is accessed with a special preamble in the

slave byte (1011) and is located at address 0FFh. It

can only be modified by performing a byte write

operation directly to the address of the register and

only one data byte is allowed for each register write

operation.

There is no need to set the WEL or RWEL in the

control register to access this fault detection register.

PUP1 PUP0 Power on Reset Delay (

PURST

)

0 0 50ms

0 1 200ms (factory setting)

1 0 400ms

1 1 800ms

WD1 WD0 Watchdog Time Out Period

0 0 1.4 seconds

0 1 200 milliseconds

1 0 25 milliseconds

1 1 disabled (factory setting)

76543210

LV1F LV2F 0 WDF 0 0 0 0

X40010, X40011, X40014, X40015

FN8111.0

March 28, 2005

Figure 6. Valid Data Changes on the SDA Bus

At power-up, the Fault Detection Register is defaulted

to all “0”. The system needs to initialize this register to

all “1” before the actual monitoring take place. In the

event of any one of the monitored sources failed. The

corresponding bits in the register will change from a

“1” to a “0” to indicate the failure. At this moment, the

system should perform a read to the register and

noted the cause of the reset. After reading the register

the system should reset the register back to all “1”

again. The state of the Fault Detection Register can be

read at any time by performing a random read at

address 0FFh, using the special preamble.

The FDR can be read by performing a random read at

OFFh address of the register at any time. Only one

byte of data is read by the register read operation.

WDF, Watchdog Timer Fail Bit (Volatile)

The WDF bit will set to “0” when the WDO

goes active.

LV1F, Low V

Reset Fail Bit (Volatile)

The LV1F bit will be set to “0” when V

(V1MON)

falls below V

TRIP1

LV2F, Low V2MON Reset Fail Bit (Volatile)

The LV2F bit will be set to “0” when V2MON falls

below V

TRIP2

SERIAL INTERFACE

Interface Conventions

The device supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all applications.

Serial Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 6.

Serial Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 6.

Serial Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the device into the Standby power mode after a read

sequence. A stop condition can only be issued after the

transmitting device has released the bus. See Figure 6.

SCL

SDA

Data Stable Data Change Data Stable

X40010, X40011, X40014, X40015

FN8111.0

March 28, 2005

Figure 7. Valid Start and Stop Conditions

Serial Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. See Figure 8.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of each subsequent eight bit word. The device

will acknowledge all incoming data and address bytes,

except for the Slave Address Byte when the Device

Identifier and/or Select bits are incorrect.

In the read mode, the device will transmit eight bits of

data, release the SDA line, then monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issue a stop condition

to return the device to Standby mode and place the

device into a known state.

Serial Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and a Word Address Byte. This gives

the master access to any one of the words in the

array. After receipt of the Word Address Byte, the

device responds with an acknowledge, and awaits the

next eight bits of data. After receiving the 8 bits of the

Data Byte, the device again responds with an

acknowledge. The master then terminates the transfer

by generating a stop condition, at which time the

device begins the internal write cycle to the nonvolatile

memory. During this internal write cycle, the device

inputs are disabled, so the device will not respond to any

requests from the master. The SDA output is at high

impedance. See Figure 9.

A write to a protected block of memory will suppress

the acknowledge bit.

Figure 8. Acknowledge Response From Receiver

SCL

SDA

Start Stop

Data Output

from

Data Output

from Receiver

81 9

Start Acknowledge

SCL from

Master

X40010, X40011, X40014, X40015

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

X40015S8I-A

Mfr. #:

Buy X40015S8I-A

Manufacturer:

Renesas / Intersil

Description:

IC VOLTAGE MONITOR DUAL 8-SOIC

Lifecycle:

New from this manufacturer.

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X40015S8I-A

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