1. The 3.3 V voltage regulator on all ColdFire+ devices powers the on-chip USB transceiver. The regulator input supports the
5 V supply typically provided by USB VBUS power.
4.3 Power modes
The V1 ColdFire CPU has two primary modes of operation, run and stop. The STOP instruction can invoke both stop and
wait modes. The CPU does not differentiate between stop and wait modes. Stop, wait, and run are augmented in a number of
ways to provide a lower-power MCU based on application needs.
The System Mode Controller (SMC) in ColdFire+ device families provides multiple power options. The Very Low Power
Run (VLPR) operating mode can drastically reduce runtime power when maximum processor frequency is not required.
Corresponding wait and stop modes are the Very Low Power Wait (VLPW) and Very Low Power Stop (VLPS) modes.
Depending on the stop requirements of the user application, a variety of stop modes are available that provide state retention,
partial power down, or full power down of certain logic and/or memory. I/O states are held in all modes of operation. The
following table compares the various power modes available.
Table 6. MCU power modes
Power mode Description Normal recovery method
Normal run Allows maximum performance of MCU. -
Normal wait Allows peripherals to function while allowing CPU to sleep,
reducing power.
Interrupt
Normal stop Places MCU in static state. Lowest power mode that retains all
registers while maintaining LVD protection.
Interrupt
VLPR (Very Low Power
Run)
Regulator in low power mode, LVD off. Maximum 2 MHz clock
source to core and 1 MHz to peripherals and flash.
1
Interrupt
VLPW (Very Low Power
Wait)
Similar to VLPR, with CPU in sleep to further reduce power. Interrupt
VLPS (Very Low Power
Stop)
Places MCU in static state, with LVD operation off. Lowest power
mode with ADC and pin interrupts functional. LPTMRs, TSI, CMP,
12-bit DAC functional.
Interrupt
LLS (Low Leakage Stop) State retention power mode. LLWU, LPTMRs, TSI, CMP, 12-bit
DAC functional. All RAM and 32-byte Register File powered.
LLWU interrupt
VLLS3 (Very Low Leakage
Stop3)
LLWU, LPTMRs, TSI, CMP, 12-bit DAC functional. All RAM and
32-byte Register File powered.
Wakeup reset
VLLS2 (Very Low Leakage
Stop2)
LLWU, LPTMRs, TSI, CMP, 12-bit DAC functional. Portion of RAM
powered off. 32-byte Register File powered.
Wakeup reset
VLLS1 (Very Low Leakage
Stop1)
LLWU, LPTMRs, TSI, CMP, 12-bit DAC functional. All RAM
powered off. 32-byte Register File powered.
Wakeup reset
1. Some peripherals, such as the UARTs, use the system clock.
The following table summarizes the operation of each module in the low power modes.
Table 7. Module operation in low power modes
Module STOP VLPR VLPW VLPS LLS VLLSx
System peripherals
CPU clock OFF 2 MHz maximum OFF OFF OFF OFF
System clock OFF 2 MHz maximum 2 MHz maximum OFF OFF OFF
Table continues on the next page...
Features
ColdFire+ Portfolio Product Brief, Rev. 4, 03/2013
Freescale Semiconductor, Inc. 11
