LPC54113J256UK49Z Datasheet LPC54113J256UK49Z | P19-P21

4.4.6.4 12-bit Digital-to-Analog Converter (DAC)

• 12-bit resolution

• Guaranteed 6-sigma monotonicity over input word

• High-speed and low-speed conversions: 1 µs conversion rate for high speed, 2 µs for low speed

• Power-down mode

• Choice of asynchronous or synchronous updates

• Automatic mode allows the DAC to generate its own output waveforms including square, triangle, and sawtooth

• Automatic mode allows programmable period, update rate, and range

• DMA support with configurable watermark level

4.4.6.5 Voltage Reference (VREF)

• Programmable trim register with 0.5 mV steps, automatically loaded with room temperature value upon reset

• Programmable mode selection:

• Off

• Bandgap out (or stabilization delay)

• Low-power buffer mode

• Tight-regulation buffer mode

• 1.2 V output at room temperature

• Dedicated output pin

Timers

4.4.7.1 FlexTimer (FTM)

• Selectable FTM source clock

• Programmable prescaler

• 16-bit counter supporting free-running or initial/final value, and counting is up or up-down

• Input capture, output compare, and edge-aligned and center-aligned PWM modes

• Input capture and output compare modes

• Operation of FTM channels as pairs with equal outputs, pairs with complementary outputs, or independent channels

with independent outputs

• Deadtime insertion is available for each complementary pair

• Generation of hardware triggers

• Software control of PWM outputs

• Configurable channel polarity

• Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition

4.4.7.2 Carrier Modulator Transmitter (CMT)

• Four modes of operation

• Time with independent control of high and low times

• Baseband

• Frequency shift key (FSK)

• Direct software control of IRO pin

• Extended space operation in time, baseband, and FSK modes

• Selectable input clock divide

• Interrupt on end of cycle

4.4.7

Timers

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• Ability to disable IRO pin and use as timer interrupt

• DMA Support

4.4.7.3 Programmable Delay Block (PDB)

• 16-bit resolution with prescaler

• Positive transition of trigger event signal initiates the counter

• Supports two triggered delay outputs signals, each with an independently controlled delay from the trigger event

• Outputs can be ORed together to schedule two conversions from one input trigger event

• Outputs can schedule precise edge placement for a pulsed output. This feature is used to generate the control signal for

the CMP's windowing feature and output to a package pin if needed for applications, such as critical conductive mode

power factor correction.

• Continuous-pulse output or single-shot mode supported

• Supports bypass mode

• Each output is independently enabled

• Seven possible trigger events

4.4.7.4 Modulo Timer (MTIM)

• 16-bit up-counter

• Free-running or 16-bit modulo

• Software controllable interrupt on overflow

• Counter reset bit (TRST)

• Counter stop bit (TSTP)

• Four software selectable clock sources for input to prescaler:

• System bus clock — rising edge

• Fixed frequency clock (XCLK) — rising edge

• External clock source on the TCLK pin — rising edge

• External clock source on the TCLK pin — falling edge

• Nine selectable clock prescale values:

• Clock source divide by 1, 2, 4, 8, 16, 32, 64, 128, or 256

4.4.7.5 Low Power Timer (LPT)

• Operation as timer or pulse counter

• Selectable clock for prescaler/glitch filter

• 1 kHz internal LPO

• External low power crystal oscillator

• Internal reference clock (not available in low leakage power modes)

• Secondary external reference clock (for example, 32 kHz crystal)

• Configurable glitch filter or prescaler with 5-bit counter

• Interrupt generated on timer compare

• Hardware trigger generated on timer compare

Communication Interfaces

4.4.8.1 USB On-the-Go Controller

• USB 1.1 and 2.0 compliant full-speed device/Host controller

4.4.8

Communication Interfaces

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• On-the-Go protocol logic

• 16 bidirectional endpoints

• DMA or FIFO data stream interfaces

• Low-power consumption

4.4.8.2 USB Device Charge Detect (DCD)

• Compliant with the latest industry standard specification, USB Battery Charging Specification, Revision 1.1

• Compatible with systems powered from:

• Rechargeable battery

• Nonrechargeable battery

• External 3.3 V LDO regulator powered from USB or directly from USB using internal regulator

• Programmable event timers for flexibility and better compatibility with future udpates to the standards

• Minimal configuration required:

• Set the clock frequency and enable the module

• Preprogrammed default values ensure compatibility with the USB Battery Charging Specification, Revision 1.1

4.4.8.3 Inter-IC Sound (I2S) / Synchronous Audio Interface (SAI)

• Support for full-duplex serial interfaces with frame synchronization such as I

S, AC97, and CODEC/DSP interfaces

• Two independent bit clock / frame sync pairs

• Four software configurable transmit or receive channels that can be software allocated to any bit clock / frame sync pair

• Independent 16 word x 32-bit FIFO per channel

• Graceful restart after FIFO Error

• Operation in stop modes

4.4.8.4 Universal Asynchronous Receiver/Transmitter (UART)

• Support for ISO 7816 protocol for interfacing with smart cards

• Full-duplex operation

• Standard mark/space non-return-to-zero (NRZ) format

• 13-bit baud rate selection with fractional divide of 32

• Programmable 8-bit or 9-bit data format

• Separately enabled transmitter and receiver

• Programmable transmitter output polarity

• Programmable receive input polarity

• 13-bit break character option

• 11-bit break character detection option

• Parameterizable buffer support for one dataword for each transmit and receive

• Independent FIFO structure for transmit and receive

• Two receiver wakeup methods:

• Idle line wakeup

• Address mark wakeup

• Address match feature in receiver to reduce address mark wakeup ISR overhead

• Ability to select MSB or LSB to be first bit on wire

• Hardware flow control support for request to send (RTS) and clear to send (CTS) signals

• Interrupt-driven operation with 11 flags:

• Transmitter data buffer at or below watermark

• Transmission complete

• Receiver data buffer at or above watermark

• Idle receiver input

• Receiver overrun

Communication Interfaces

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P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

LPC54113J256UK49Z

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NXP Semiconductors

Description:

ARM Microcontrollers - MCU LPC54113J256UK49/UNCASED///REEL 7 Q1 DP CHIPS

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LPC54113J256UK49Z