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m39l0rx0x0x0U3.fm - Rev. D 9/13 EN
5 ©2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb NOR Flash and 128Mb, 512Mb LPDDR MCP
Signal Descriptions
Signal Descriptions
Flash Memory Address Inputs (ADQ
F
[15:0] and A
F
[MAX:16])
The address inputs select the cells in the Flash memory array to access during bus READ
operations. During bus WRITE operations they control the commands sent to the
command interface of the Flash memory’s program/erase controller.
A
F
MAX is A
F
23 for 256Mb Flash memory and it is A
F
22 for 128Mb Flash memory.
FLash Memory Data I/Os (ADQ
F
[15:0])
The Flash memory data I/O output the data stored at the selected address during a bus
READ operation or input a command or the data to be programmed during a bus WRITE
operation.
Flash Memory Chip Enable (E
F
)
The chip enable input activates the Flash memory control logic, input buffers, decoders
and sense amplifiers. When chip enable is at V
IL
and reset is at V
IH
, the device is in active
mode. When chip enable is at V
IH
the memory is deselected, the outputs are High-Z, and
the power consumption is reduced to the standby level.
Flash Memory Output Enable (G
F
)
The output enable input controls data outputs during the bus READ operation of the
memory.
Flash Memory Write Enable (W
F
)
The write enable input controls the bus WRITE operation of the memory’s command
interface. The data and address inputs are latched on the rising edge of chip enable or
write enable, whichever occurs first.
Flash Memory RESET (RP
F
)
Reset provides a hardware reset of the memory. When reset is at V
IL
, the memory is in
reset mode, where the outputs are High-Z, and the current consumption is reduced to
the reset supply current I
DD2
. Refer to the M58LRxxxKCD data sheet for the value of I
DD2
.
After reset, all blocks are in the locked state and the configuration register is reset. When
reset is at V
IH
, the device is in normal operation. Upon exiting reset mode, the device
enters asynchronous read mode, but a negative transition of chip enable or latch enable
is required to ensure valid data outputs.
Flash Memory Write Protect (WP
F
)
Write protect is an input that provides an additional hardware protection for each block.
When write protect is at V
IL
, the lock-down is enabled and the protection status of the
locked-down blocks cannot be changed. When write protect is at V
IH
, the lock-down is
disabled and the locked-down blocks can be locked or unlocked (refer to the
M58LRxxxKCD data sheet).
Flash Memory Clock (K
F
)
The clock input synchronizes the memory to the microcontroller during synchronous
READ operations; the address is latched on a clock edge (rising or falling, according to
the configuration settings) when latch enable is at V
IL
. Clock is ignored during asynchro-
nous READ and in WRITE operations.
