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m39l0rx0x0x0U3.fm - Rev. D 9/13 EN
7 ©2011 Micron Technology, Inc. All rights reserved.
128Mb, 256Mb NOR Flash and 128Mb, 512Mb LPDDR MCP
Signal Descriptions
–If A
D
10 is HIGH (set to 1), the read or write operation includes an auto precharge
cycle.
–If A
D
10 is Low (set to ‘0’), the READ or WRITE cycle does not include an auto pre-
charge cycle.
• When issuing a PRECHARGE command:
–If A
D
10 is LOW, only the bank selected by BA
D
[1:0] is precharged.
–If A
D
10 is HIGH, all the banks are precharged.
The address inputs are latched at the cross point of K
D
rising edge and K
D
falling edge.
LPDDR Data I/Os (DQ
D
[15:0])
The LPDDR data I/O output the data stored at the selected address during a READ oper-
ation, or to input the data during a WRITE operation.
LPDDR Bank Select Address Inputs (BA
D
[1:0])
The bank select address inputs, BA
D
0 and BA
D
1, select the LPDDR bank to be made
active (see the M65KGxxxAM data sheet for details).
When selecting the addresses, the device must be enabled, the row address strobe, RAS
D
,
must be LOW, V
IL
, the column address strobe, CAS
D
, and W
D
must be HIGH, V
IH
.
LPDDR Clock Inputs (K
D
, K
D
)
The clock signals, K
D
and K
D
, are the master clock inputs. All input signals except
UDQM
D
/LDQM
D
, UDQS
D
/LDQS
D
and DQ
D
[15:0] are referred to the cross point of K
D
rising edge and K
D
falling edge. During READ operations, UDQS
D
/LDQS
D
and
DQ
D
[15:0] are referred to the crosspoint of K
D
rising edge and K
D
falling edge. During
WRITE operations, UDQM
D
/LDQM
D
and DQ
D
[15:0] are referred to the crosspoint of
UDQS
D
/LDQS
D
and VREF, and UDQS
D
/LDQS
D
to the crosspoint of K
D
rising edge and
K
D
falling edge.
LPDDR Clock Enable (KE
D
)
When driven LOW, V
IL
, the clock enable input, KE
D
, is used to suspend the Clock K
D
, to
switch the device to self refresh or power-down.
The clock enable, KE
D
, must be stable for at least one clock cycle. This means that if KE
D
level changes on K
D
rising edge and K
D
falling edge with a setup time of
t
AS, it must be at
the same level by the next K
D
rising edge with a hold time of
t
AH.
LPDDR Chip Enable (E
D
)
The chip enable input, E
D
, activates the memory state machine, address buffers and
decoders when driven Low, V
IL
. When E
D
is High, V
IH
, the device is not selected.
LPDDR Write Enable (W
D
)
The write enable input, W
D
, controls writing.
LPDDR Row Address Strobe (RAS
D
)
The row address strobe, RAS
D
, is used in conjunction with address inputs A
D
[MAX:0]
and BA
D
[1:0], to select the starting address location prior to a READ or WRITE operation.
