X9410WS24ZT1 Datasheet X9410YS24Z, X9410WS24ZT1, X9410WV24Z | P1-P3

FN8193.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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X9410

Low Noise/Low Power/SPI Bus

Dual Digitally Controlled Potentiometer

(XDCP™)

FEATURES

• Two potentiometers per package

• SPI serial interface

• Register oriented format

- Direct read/write/transfer wiper positions

- Store as many as four positions per

potentiometer

• Power supplies

-V

= 2.7V to 5.5V

- V+ = 2.7V to 5.5V

- V- = -2.7V to -5.5V

• Low power CMOS

- Standby current < 1µA

- High reliability

- Endurance - 100,000 data changes per bit per

- Register data retention - 100 years

• 8-bytes of nonvolatile EEPROM memory

•10kresistor arrays

• Resolution: 64 taps each pot

• 24 Ld SOIC, 24 Ld TSSOP, and 24 Ld plastic DIP

packages

• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION

The X9410 integrates two digitally controlled

potentiometers (XDCPs) on a monolithic CMOS

integrated circuit.

The digitally controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the SPI

serial bus interface. Each potentiometer has

associated with it a volatile Wiper Counter Register

(WCR) and four nonvolatile Data Registers (DR0:DR3)

that can be directly written to and read by the user.

The contents of the WCR controls the position of the

wiper on the resistor array through the switches.

Power-up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

R0 R1

R2 R3

Wiper

Counter

(WCR)

Resistor

Array

Pot1

R0 R1

R2 R3

Wiper

Counter

(WCR)

Interface

and

Control

Circuitry

SCK

Data

HOLD

Pot 0

V+

V-

Pot 1

Data Sheet October 12, 2006

FN8193.2

October 12, 2006

PIN DESCRIPTIONS

Host Interface Pins

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked

out by the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the pots and pot

registers are input on this pin. Data is latched by the

rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the

X9410.

Chip Select (CS

)

When CS

is HIGH, the X9410 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device will be in the

standby state. CS

LOW enables the X9410, placing it

in the active power mode. It should be noted that after

a power-up, a HIGH to LOW transition on CS

required prior to the start of any operation.

Hold (HOLD

)

HOLD

is used in conjunction with the CS pin to select

the device. Once the part is selected and a serial

sequence is underway, HOLD

may be used to pause

the serial communication with the controller without

resetting the serial sequence. To pause, HOLD

must

be brought LOW while SCK is LOW. To resume

communication, HOLD

is brought HIGH, again while

SCK is LOW. If the pause feature is not used, HOLD

should be held HIGH at all times.

Device Address (A

- A

)

The address inputs are used to set the least significant

2 bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

address input in order to initiate communication with

the X9410. A maximum of 4 devices may occupy the

SPI serial bus.

Ordering Information

PART NUMBER PART MARKING

LIMITS

(V)

POTENTIOMETER

ORGANIZATION

(k)

TEMP RANGE

(°C) PACKAGE PKG. DWG. #

X9410YS24I X9410YS I 5 ±10% 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3

X9410YS24IZ (Note) X9410YS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027

X9410WP24I X9410WP I 10 -40 to 85 24 Ld PDIP E24.6

X9410WS24I* X9410WS I -40 to 85 24 Ld SOIC (300 mil) M24.3

X9410WS24IZ* (Note) X9410WS ZI -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027

X9410WV24I* X9410WV I -40 to 85 24 Ld TSSOP (4.4mm) MDP0044

X9410WV24IZ* (Note) X9410WV ZI -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9410YS24I-2.7 X9410YS G 2.7 to 5.5 2.5 -40 to 85 24 Ld SOIC (300 mil) M24.3

X9410YS24IZ-2.7 (Note) X9410YS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027

X9410WP24I-2.7 X9410WP G 10 -40 to 85 24 Ld PDIP E24.6

X9410WS24I-2.7* X9410WS G -40 to 85 24 Ld SOIC (300 mil) M24.3

X9410WS24IZ-2.7* (Note) X9410WS ZG -40 to 85 24 Ld SOIC (300 mil) (Pb-free) MDP0027

X9410WV24-2.7* X9410WV F 0 to 70 24 Ld TSSOP (4.4mm) MDP0044

X9410WV24Z-2.7* (Note) X9410WV ZF 0 to 70 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

X9410WV24I-2.7* X9410WV G -40 to 85 24 Ld TSSOP (4.4mm) MDP0044

X9410WV24IZ-2.7* (Note) X9410WV ZG -40 to 85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X9410

FN8193.2

October 12, 2006

Potentiometer Pins

- V

), V

- V

)

The V

and V

inputs are equivalent to the terminal

connections on either end of a mechanical potentiometer.

- V

)

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

Hardware Write Protect Input (WP

)

The WP

pin when LOW prevents nonvolatile writes to

the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for

the XDCP analog section.

PIN CONFIGURATION

PIN NAMES

DEVICE DESCRIPTION

The X9410 is a highly integrated microcircuit

incorporating two resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

Serial Interface

The X9410 supports the SPI interface hardware

conventions. The device is accessed via the SI input

with data clocked in on the rising SCK. CS

must be

LOW and the HOLD

and WP pins must be HIGH

during the entire operation.

The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce

system pin count.

Array Description

The X9410 is comprised of two resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the fixed terminals of a mechanical

potentiometer (V

and V

inputs).

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter

to select, and enable, one of sixty-four switches.

V+

HOLD

SCK

DIP/SOIC

X9410

V-

TSSOP

X9410

HOLD

SCK

V+

V-

Symbol Description

SCK Serial Clock

, S

Serial Data

- A

Device Address

- V

Potentiometer Pins

(terminal equivalent)

- V

Potentiometer Pin

(wiper equivalent)

Hardware Write Protection

V+,V- Analog Supplies

System Supply Voltage

System Ground

NC No Connection

X9410

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

X9410WS24ZT1

Mfr. #:

Buy X9410WS24ZT1

Manufacturer:

Renesas / Intersil

Description:

Digital Potentiometer ICs DL XDCP 10KOHM 64 TAP SPI

Lifecycle:

New from this manufacturer.

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X9410WS24ZT1

X9410WS24ZT1

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