13
FN8193.2
October 12, 2006
HIGH-VOLTAGE WRITE CYCLE TIMING
XDCP TIMING
SYMBOL TABLE
TIMING DIAGRAMS
Input Timing
Symbol Parameter Typ. Max. Unit
t
WR
High-voltage write cycle time (store instructions) 5 10 ms
Symbol Parameter Min. Max. Unit
t
WRPO
Wiper response time after the third (last) power supply is stable 10 µs
t
WRL
Wiper response time after instruction issued (all load instructions) 10 µs
t
WRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
...
CS
SCK
SI
SO
MSB LSB
High Impedance
t
LEAD
t
H
t
SU
t
FI
t
CS
t
LAG
t
CYC
t
WL
...
t
RI
t
WH
X9410
14
FN8193.2
October 12, 2006
Output Timing
Hold Timing
XDCP Timing (for All Load Instructions)
...
CS
SCK
SO
SI
ADDR
MSB LSB
t
DIS
t
HO
t
V
...
...
CS
SCK
SO
SI
HOLD
t
HSU
t
HH
t
LZ
t
HZ
t
HOLD
t
RO
t
FO
...
CS
SCK
SI
MSB LSB
V
W
/R
W
t
WRL
...
SO
High Impedance
X9410
15
FN8193.2
October 12, 2006
XDCP Timing (for Increment/Decrement Instruction)
Write Protect and Device Address Pins Timing
...
CS
SCK
SO
SI
ADDR
t
WRID
High Impedance
V
W
/R
W
...
Inc/Dec
Inc/Dec
...
CS
WP
A0
A1
t
WPASU
t
WPAH
(Any Instruction)
X9410

X9410WS24ZT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs DL XDCP 10KOHM 64 TAP SPI
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union