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AD9956YCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
AD9956
Rev. A | Page 29 of 32
CFR1<3> = 0 (default). The automatic synchronization function
of the DDS core is disabled.
CFR1<3> = 1. The automatic synchronization function is on.
The device is slaved to an external reference and adjusts the
internal SYNC_CLK to match the external reference, which is
supplied on the SYNC_IN input.
CFR1<2> Software Manual Synchronization
Rather than relying on the part to automatically synchronize the
internal clocks, the user can program the part to advance the
internal SYNC_CLK one system clock cycle. This bit is self
clearing and can be set multiple times.
CFR1<2> = 0 (default). The SYNC_CLK stays in the current
timing relationship to SYSCLK.
CFR1<2> = 1. The SYNC_CLK advances the rising and falling
edges by one SYSCLK cycle. This bit is then self-cleared.
CFR1<1> Hardware Manual Synchronization
Similar to the software manual synchronization (CFR1<2>),
this function enables the user to advance the SYNC_CLK rising
edge by one system clock period. This bit enables the
PLL_LOCK/SYNC_IN pin as a digital input. Once enabled,
every rising edge on the SYNC_IN input advances the
SYNC_CLK by one SYSCLK period. While enabled, the
PLL_LOCK signal is not available on an external pin. However,
loop out-of-lock events trigger a flag in the control register
(CFR1<24>).
CFR1<1> = 0 (default). The hardware manual synchronization
function is disabled. Either the part is outputting the
PLL_LOCK (CFR1<3> = 0), or it is using the SYNC_IN to slave
the SYNC_CLK signal to an external reference provided on
SYNC_IN (CFR1<3> = 1).
CFR1<1> = 1. PLL_LOCK/SYNC_IN is set as a digital input.
Each subsequent rising edge on this pin advances the
SYNC_CLK rising edge by one SYSCLK period.
CFR1<0> High Speed Synchronization Enable Bit
This bit enables extra functionality in the auto synchronization
algorithm, which enables the device to synchronize high speed
clocks (SYNC_CLK > 62.5 MHz).
CFR1<0> = 0 (default). High speed synchronization is disabled.
CFR1<0> = 1. High speed synchronization is enabled.
Control Function Register 2 (CFR2)
This control register is comprised of five bytes, which must be
written during a write operation involving CFR2. With some
minor exceptions, the CFR2 primarily controls analog and tim-
ing functions on the AD9956.
CFR2<39> DAC Power-Down Bit
This bit powers down the DAC portion of the AD9956 and puts
it into the lowest power dissipation state.
CFR2<39> = 0 (default). DAC is powered on and operating.
CFR2<39> = 1. DAC is powered down and the output is in a
high impedance state.
CFR2<38> to CFR2<34> Open
Unused locations. Write a Logic 0.
CFR2<33> Internal Band Gap Power-Down
To shut off all internal quiescent current, the band gap needs to
be powered down. This is normally not done because it takes a
long time (~10 ms) for the band gap to power up and settle to
its final value.
CFR2<33> = 0. Even when all other sections are powered down,
the band gap is powered up and is providing a regulated voltage.
CFR2<33> = 1. The band gap is powered down.
CFR2<32> Internal CML Driver DRV_RSET
To program the CML driver’s output current, a resistor
must be placed between the DRV_RSET pin and ground. This
bit enables an internal resistor to program the output current of
the driver.
CFR2<32> = 0 (default). The DRV_RSET pin is enabled,
and an external resistor must be attached to the CP_RSET pin
to program the output current.
CFR2<32> = 1. The CML current is programmed by the inter-
nal resistor and ignores the resistor on the DRV_REST pin.
CFR2<31:29> Clock Driver Rising Edge
These bits control the slew rate of the CML clock driver output’s
rising edge. When these bits are on, additional current is sent to
the output driver to increase the rising edge slew rate capability;
the contributions of each bit are cumulative. Table 6 describes
how the bits increase the current. Note that the additional cur-
rent is on only during the rising edge of the waveform for ap-
proximately 250 ps, but not on during the entire transition.
Table 6. CML Clock Driver Rising Edge Slew Rate
Control Bits and Associated Surge Current
CFR2<31> = 1 7.6 mA
CFR2<30> = 1 3.8 mA
CFR2<29> = 1 1.9 mA
AD9956
Rev. A | Page 30 of 32
CFR2<28:26> Clock Driver Falling Edge Control
These bits control the slew rate of the CML clock driver output’s
falling edge. When these bits are on, additional current is sent to
the output driver to increase the rising edge slew rate capability.
Table 7 describes how the bits increase the current; the contri-
butions of each bit are cumulative. Note that the additional cur-
rent is on only during the rising edge of the waveform, for ap-
proximately 250 ps, but not on during the entire transition.
Table 7. CML Clock Drive Falling Edge Slew Rate
Control Bits and Associated Surge Current
CFR2<28> = 1 5.4 mA
CFR2<30> = 1 2.7 mA
CFR2<29> = 1 1.35 mA
CFR2<25> PLL_LOCK_DETECT Enable
This bit enables the PLL_LOCK/SYNC_IN pin as a lock detect
output for the PLL.
CFR2<25> = 0 (default).The PLL_LOCK_DETECT signal is
disabled.
CFR2<25> = 1. The PLL_LOCK_DETECT signal is enabled.
CFR2<24> PLL_LOCK_DETECT Mode
This bit toggles the modes of the PLL_LOCK_DETECT func-
tion. The lock detect can either be a status indicator (locked or
unlocked), or it can indicate a lead-lag relationship between the
two phase frequency detector inputs.
CFR2<24> = 0 (default). The lock detect acts as a status indica-
tor (PLL is locked 0 or unlocked 1).
CFR2<24> = 1. The lock detect acts as a lead/lag indicator. A
1 on the PLL_LOCK pin means that the PLLOSC pin lags the
reference. A 0 means that the PLLOSC pin leads the reference.
CFR2<23> RF Divider Power-Down
This bit powers the RF divider down to save power when not in
used.
CFR2<23> = 0 (default). RF divider is on.
CFR2<23> = 1. RF divider is powered down and an alternate
path between the REFCLK inputs and SYSCLK is enabled.
CFR2<22:21> RF Divider Ratio
These two bits control the RF divider ratio (÷R).
CFR2<22:21> = 11 (default). RF Divider R = 8.
CFR2<22:21> = 10. RF Divider R= 4.
CFR2<22:21> = 01. RF Divider R = 2.
CFR2<22:21> = 00. RF Divider R = 1. Note that this is not the
same as bypassing the RF divider.
CFR2<20> Clock Driver Power-Down
This bit powers down the CML clock driver circuit.
CFR2<20> =1 (default). CML clock driver circuit is powered down.
CFR2<20> = 0. CML clock driver is powered up.
CFR2<19:18> Clock Driver Input Select
These bits control the mux on the input for the CML clock driver.
CFR2<19:18> = 00. The CML clock driver is disconnected from
all inputs (and does not toggle).
CFR2<19:18> = 01. The CML clock driver is driven by the
PLLOSC input pin.
CFR2<19:18> = 10 (default). The CML clock driver is driven by
the output of the RF divider.
CFR2<19:18> = 11. The CML clock driver is driven by the input
of the RF divider
CFR2<17> Slew Rate Control Bit
Even without the additional surge current supplied by the rising
edge slew rate control bits and the falling edge slew rate control
bits, the device applies a default 7.6 mA surge current to the
rising edge and a 4.05 mA surge current to the falling edge. This
bit disables all slew rate enhancement surge current, including
the default values.
CFR2<17> = 0 (default). The CML driver applies default surge
current to rising and falling edges.
CFR2<17> = 1. Driver applies no surge current during transi-
tions. The only current is the continuous current.
CFR2<16> RF Divider SYSCLK Mux Bit
This bit toggles the mux to control whether the RF divider out-
put or input is supplying SYSCLK to the device.
CFR2<16> = 0 (default). The RF divider output supplies the
DDS SYSCLK.
CFR2<16> = 1. The RF divider input supplies the DDS SYSCLK
(bypass the divider). Note that regardless of the condition of the
configuration of the clock input, the DDS SYSCLK must not
exceed the maximum rated clock speed.
AD9956
Rev. A | Page 31 of 32
CFR2<15:12> PLLREF Divider Control Bits (÷N)
These 4 bits set the PLLREF divider (÷N) ratio where N is a
value equal to 1 to 16. CFR2<15:12> = 0000 means that
N = 1 and CFR2<15:12> = 1111 means that N = 16, or simply,
N = CFR2<15:12> + 1.
CFR2<15:12> = N = CFR2<15:12> = N =
0000 1 1000 9
0001 2 1001 10
0010 3 1010 11
0011 4 1011 12
0100 5 1100 13
0101 6 1101 14
0110 7 1110 15
0111 8 1111 16
CFR2<11:8> PLLREF Divider Control Bits (÷M)
These 4 bits set the PLLOSC divider (÷M) ratio where
M is a value equal to 1 to 16. CFR2<11:8> = 0000 means
that M = 1 and CFR2<11:8> = 1111 means that M = 16, or
M = CFR2<11:8> + 1.
CFR2<11:8> = M = CFR2<11:8> = M =
0000 1 1000 9
0001 2 1001 10
0010 3 1010 11
0011 4 1011 12
0100 5 1100 13
0101 6 1101 14
0110 7 1110 15
0111 8 1111 16
CFR2<7:6> Open
Unused locations. Write a Logic 0.
CFR2<5> CP Polarity
This bit sets the polarity of the charge pump, in response to a
ground referenced or a supply referenced VCO.
CFR2<5> = 0 (default). The charge pump is configured to
operate with a supply referenced VCO. If PLLOSC lags PLLREF,
the charge pump will attempt to drive the VCO control node
voltage higher. If PLLOSC leads PLLREF, the charge pump will
attempt to drive the VCO control node voltage lower.
CFR2<5> = 1. The charge pump is configured to operate with a
ground referenced VCO. If PLLOSC lags PLLREF, the charge
pump will attempt to drive the VCO control node voltage lower.
If PLLOSC leads PLLREF, the charge pump will attempt to drive
the VCO control node voltage higher.
CFR2<4> Charge Pump Full Power-Down
This bit, when set, will put the charge pump into a full power-
down mode.
CFR2<4> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<4> = 1. The charge pump is completely powered down.
CFR2<3> Charge Pump Quick Power-Down
Rather than power down the charge pump, which can take a
long time to recover from, a quick power-down mode, which
powers down only the charge pump output buffer, is included.
While this doesn’t reduce the power consumption significantly,
it does shut off the output to the charge pump and allows it to
come back on in a rapidly.
CFR2<3> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<3> = 1. The charge pump is on and running, but the
output buffer is powered down.
CFR2<2:0> Charge Pump Current Scale.
A base output current from the charge pump is determined by a
resistor connected from the CP_RSET pin to ground (see the
PLL Circuitry section). However, it is possible to multiply the
charge pump output current by a value from 1:8 by programming
these bits. The charge pump output current is scaled by
CFR2<2:0> +1.
CFR2<2:0> = 000 (default). Scale factor = 1 to CFR2<2:0> = 111 (8).
CFR2<2:0> Scale Factor
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

AD9956YCPZ

Mfr. #:
Buy AD9956YCPZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 400 MSPS 14-Bit 1.8V CMOS
Lifecycle:
New from this manufacturer.
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