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AD9956YCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
AD9956
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Product Overview............................................................................. 3
Specifications..................................................................................... 4
Loop Measurement Conditions.................................................. 9
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Typical Application Circuits .......................................................... 16
Application Circuit Explanations............................................. 17
General Description....................................................................... 18
DDS Core..................................................................................... 18
PLL Circuitry .............................................................................. 18
CML Driver................................................................................. 19
Modes of Operation ....................................................................... 20
DDS Modes of Operation ......................................................... 20
Synchronization Modes for Multiple Devices .............................. 20
Serial Port Operation..................................................................... 22
Instruction Byte .......................................................................... 23
Serial Interface Port Pin Description....................................... 23
MSB/LSB Transfers .................................................................... 23
Register Map and Description ...................................................... 24
Control Function Register Descriptions ................................. 27
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to the Pin Configuration................................................ 11
Changes to the Pin Function Descriptions ................................. 12
Changes to Table 5.......................................................................... 24
Changes to CFR2<15:12> PLLREF Divider
Control Bits (÷N)............................................................................ 31
Changes to CFR2<11:8> PLLREF Divider
Control Bits (÷M)........................................................................... 31
Changes to Ordering Guide .......................................................... 32
7/04—Revision: Initial Version
AD9956
Rev. A | Page 3 of 32
PRODUCT OVERVIEW
The AD9956 is Analog Devices’ newest AgileRF synthesizer.
The device is comprised of DDS and PLL circuitry. The DDS
features a 14-bit DAC operating at up to 400 MSPS and a 48-bit
frequency tuning word (FTW). The PLL circuitry includes a
phase frequency detector with scaleable 200 MHz inputs
(divider inputs operate up to 655 MHz) and digital control over
the charge pump current. The device also includes a 655 MHz
CML-mode PECL-compliant driver with programmable slew
rates. The AD9956 uses advanced DDS technology, an internal
high speed, high performance DAC, and an advanced phase
frequency detector/charge pump combination, which, when
used with an external VCO, enables the synthesis of digitally
programmable, frequency-agile analog output sinusoidal wave-
forms up to 2.7 GHz. The AD9956 is designed to provide fast
frequency hopping and fine tuning resolution (48-bit frequency
tuning word). Information is loaded into the AD9956 via a
serial I/O port that has a device write-speed of 25 Mb/s. The
AD9956 DDS block also supports a user-defined linear sweep
mode of operation.
The AD9956 is specified to operate over the extended
automotive range of −40°C to +125°C.
AD9956
Rev. A | Page 4 of 32
SPECIFICATIONS
AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ T
A
= 25°C) DAC_R
SET
= 3.92 kΩ, CP_R
SET
= 3.09 kΩ,
DRV_R
SET
= 4.02 kΩ, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
RF DIVIDER (REFCLK ) INPUT SECTION (÷R)
RF Divider Input Range 1 2700 MHz
DDS SYSCLK not to exceed
400 MSPS
Input Capacitance (DC) 3 pF
Input Impedance (DC) 1500 Ω
Input Duty Cycle 42 50 58 %
Input Power/Sensitivity −10 +4 dBm Single-ended, into a 50 Ω load
1
Input Voltage Level 350 1000 mV p-p
PHASE FREQUENCY DETECTOR/CHARGE PUMP
PLLREF Input
Input Frequency
2
÷M Set to Divide by at Least 4 655 MHz
÷M Bypassed 200 MHz
Input Voltage Levels 200 450 600 mV p-p
Input Capacitance 10 pF
Input Resistance 1500 Ω
PLLOSC Input
Input Frequency
÷N Set to Divide by at Least 4 655 MHz
÷N Bypassed 200 MHz
Input Voltage Levels 200 450 600 mV p-p
Input Capacitance 10 pF
Input Resistance 1500 Ω
Charge Pump Source/Sink Maximum Current 4 mA
Charge Pump Source/Sink Accuracy −15 +5 %
Charge Pump Source/Sink Matching −5 +5 %
Charge Pump Output Compliance Range
3
0.5 CP_VDD − 0.5 V
PLL_LOCK Drive Strength 2 mA
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency 149 dBc/Hz
@ 2 MHz PFD Frequency 133 dBc/Hz
@ 100 MHz PFD Frequency 116 dBc/Hz
@ 200 MHz PFD Frequency 113 dBc/Hz
CML OUTPUT DRIVER (DRV)
Differential Output Voltage Swing
4
720 mV 50 Ω load to supply, both lines
Maximum Toggle Rate 655 MHz
Common-Mode Output Voltage 1.75 V
Output Duty Cycle 42 50 58 %
Output Current
Continuous
5
7.2 mA
Rising Edge Surge 20.9 mA
Falling Edge Surge 13.5 mA
Output Rise Time 250 ps 100 Ω terminated, 5 pF load
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AD9956YCPZ

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Buy AD9956YCPZ
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 400 MSPS 14-Bit 1.8V CMOS
Lifecycle:
New from this manufacturer.
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