AD9956
Rev. A | Page 5 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS (SDI/O, I/O_RESET, RESET,
I/O_UPDATE, PS0 to PS2, SYNC_IN)
V
IH
, Input High Voltage 2.0 V
V
IL
, Input Low Voltage 0.8 V
I
INH
, I
INL
Input Current ±1 ±5 µA
C
IN
, Maximum Input Capacitance 3 pF
LOGIC OUTPUTS (SDO, SYNC_OUT, PLL_LOCK)
6
V
OH
, Output High Voltage 2.7 V
V
OH
, Output Low Voltage 0.4 V
I
OH
100 µA
I
OL
100 µA
POWER CONSUMPTION
Total Power Consumed, All Functions On 400 mW
IAVDD 85 mA
IDVDD 45 mA
IDVDD_I/O 20 mA
ICP_VDD 15 mA
Power-Down Mode 80 mW
WAKE-UP TIME (from Power-Down Mode)
Digital Power-Down (CFR1<7>) 12 ns
DAC Power-Down (CFR2<39>) 7 µs
RF Divider Power-Down (CFR2<23>) 400 ns
Clock Driver Power-Down (CFR2<20>) 6 µs
Charge Pump Full Power-Down (CFR2<4>) 10 µs
Charge Pump Quick Power-Down (CFR2<3>) 150 ns
DAC OUTPUT CHARACTERISTICS
Resolution 14 Bits
Full-Scale Output Current 10 15 mA
Gain Error −10 +10 % FS
Output Offset 0.6 µA
Output Capacitance 5 pF
Voltage Compliance Range AVDD 0.50 AVDD + 0.50 V
Wideband SFDR (DC to Nyquist)
10 MHz Analog Out −64 dBc
40 MHz Analog Out −62 dBc
80 MHz Analog Out −60 dBc
120 MHz Analog Out −55 dBc
160 MHz Analog Out −55 dBc
Narrowband SFDR
10 MHz Analog Out (±1 MHz) −89 dBc
10 MHz Analog Out (±250 kHz) −91 dBc
10 MHz Analog Out (±50 kHz) −93 dBc
40 MHz Analog Out (±1 MHz) −87 dBc
40 MHz Analog Out (±250 kHz) −89 dBc
40 MHz Analog Out (±50 kHz) −91 dBc
80 MHz Analog Out (±1 MHz) −85 dBc
80 MHz Analog Out (±250 kHz) −87 dBc
80 MHz Analog Out (±50 kHz) −89 dBc
120 MHz Analog Out (±1 MHz) −83 dBc
120 MHz Analog Out (±250 kHz) −85 dBc
120 MHz Analog Out (±50 kHz) −87 dBc
AD9956
Rev. A | Page 6 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
160 MHz Analog Out (±1 MHz) −81 dBc
160 MHz Analog Out (±250 kHz) −83 dBc
160 MHz Analog Out (±50 kHz) −85 dBc
DAC Residual Phase Noise
19.7 MHz F
OUT
@ 10 Hz Offset 125 dBc/Hz
@ 100 Hz Offset 135 dBc/Hz
@ 1 kHz Offset 143 dBc/Hz
@ 10 kHz Offset 152 dBc/Hz
@ 100 kHz Offset 158 dBc/Hz
>1 MHz Offset 163 dBc/Hz
51.84 MHz F
OUT
@ 10 Hz Offset 119 dBc/Hz
@ 100 Hz Offset 125 dBc/Hz
@ 1 kHz Offset 132 dBc/Hz
@ 10 kHz Offset 142 dBc/Hz
@ 100 kHz Offset 150 dBc/Hz
>1 MHz Offset 155 dBc/Hz
105.3 MHz Analog Out
@ 10 Hz Offset 105 dBc/Hz
@ 100 Hz Offset 115 dBc/Hz
@ 1 kHz Offset 122 dBc/Hz
@ 10 kHz Offset 131 dBc/Hz
@ 100 kHz Offset 139 dBc/Hz
>1 MHz Offset 142 dBc/Hz
155.52 MHz Analog Out
@ 10 Hz Offset 105 dBc/Hz
@ 100 Hz Offset 110 dBc/Hz
@ 1 kHz Offset 119 dBc/Hz
@ 10 kHz Offset 127 dBc/Hz
@ 100 kHz Offset 135 dBc/Hz
>1 MHz Offset 142 dBc/Hz
CRYSTAL OSCILLATOR (ON PLLREF INPUT)
Operating Range 20 25 30 MHz
Residual Phase Noise (@ 25 MHz)
@ 10 Hz Offset 95 dBc/Hz
@ 100 Hz Offset 120 dBc/Hz
@ 1 kHz Offset 137 dBc/Hz
@ 10 kHz Offset 156 dBc/Hz
@ 100 kHz Offset 164 dBc/Hz
>1 MHz Offset 170 dBc/Hz
DIGITAL TIMING SPECIFICATIONS
CS
to SCLK Setup Time TPRE
6 ns
Period of SCLK (Write Speed) TSCLKW 40 ns
Period of SCLK (Read Speed) TSCLKR 400 ns
Serial Data Setup Time TDSU 6.5 ns
Serial Data Hold Time TDHLD 0 ns
TDV Data Valid Time TDV 40 ns
I/O Update to SYNC_CLK Setup Time TUD 7 ns
PS<2:0> to SYNC_CLK Setup Time TPS 7 ns
AD9956
Rev. A | Page 7 of 32
Parameter Min Typ Max Unit Test Conditions/Comments
Latencies/Pipeline Delays
7
I/O Update to DAC Frequency Change 33 SYSCLK Cycles
I/O Update to DAC Phase Change 33 SYSCLK Cycles
PS<2:0> to DAC Frequency Change 29 SYSCLK Cycles
PS<2:0> to DAC Phase Change 29 SYSCLK Cycles
I/O Update to CP_OUT Scaler Change 4 SYSCLK Cycles
I/O Update to Frequency Accumulator
Step Size Change
4 SYSCLK Cycles
I/O Update to Frequency Accumulator
Ramp Rate Change
4 SYSCLK Cycles
RF DIVIDER/CML DRIVER EQUIVALENT
INTRINSIC TIME JITTER
F
IN
= 414.72 MHz, F
OUT
= 51.84 MHz
BW = 12 kHz −> 400 kHz 136 f
S
rms OC1, RF Divider R = 8
F
IN
= 1244.16 MHz, F
OUT
= 155.52 MHz
BW = 12 kHz −> 1.3 MHz 101 f
S
rms OC3, RF Divider R = 8
F
IN
= 2488.32 MHz, F
OUT
= 622.08 MHz
BW = 12 kHz −> 5 MHz 108 f
S
rms OC12, RF Divider R = 4
RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE
F
IN
= 157.6 MHz, F
OUT
= 19.7 MHz RF Divider R = 8
@ 10 Hz −115 dBc/Hz
@ 100 Hz −126 dBc/Hz
@ 1 kHz −134 dBc/Hz
@ 10 kHz −143 dBc/Hz
@ 100 kHz −150 dBc/Hz
> 1 MHz −151 dBc/Hz
F
IN
= 1240 MHz, F
OUT
= 155 MHz RF Divider R = 8
@ 10 Hz −111 dBc/Hz
@ 100 Hz −122 dBc/Hz
@ 1 kHz −129 dBc/Hz
@ 10 kHz −138 dBc/Hz
@ 100 kHz −146 dBc/Hz
@ 1 MHz −150 dBc/Hz
>3 MHz −153 dBc/Hz
F
IN
= 2488MHz, F
OUT
= 622 MHz RF Divider R = 4
@ 10 Hz −97 dBc/Hz
@ 100 Hz −110 dBc/Hz
@ 1 kHz −120 dBc/Hz
@ 10 kHz −126 dBc/Hz
@ 100 kHz −136 dBc/Hz
@ 1 MHz −141 dBc/Hz
>3 MHz −144 dBc/Hz
TOTAL SYSTEM TIME JITTER FOR 622 MHz CLOCK
See the Loop Measurement Condi-
tions section
12 kHz to 5 MHz Bandwidth 0.7 ps rms

AD9956YCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 400 MSPS 14-Bit 1.8V CMOS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet