Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. D
06/21/2011
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IS61WV12816DALL/DALS
IS61WV12816DBLL/DBLS
IS64WV12816DBLL/DBLS
FEATURES
HIGH SPEED: (IS61/64WV12816DALL/DBLL)
• High-speed access time: 8, 10, 12, 20 ns
• Low Active Power: 135 mW (typical)
• Low Standby Power: 12 μW (typical)
CMOS standby
LOW POWER: (IS61/64WV12816DALS/DBLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 55 mW (typical)
• Low Standby Power: 12 μW (typical)
CMOS standby
• Single power supply
— V
DD 1.65V to 2.2V (IS61WV12816DAxx)
— V
DD 2.4V to 3.6V (IS61/64WV12816DBxx)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
128K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM
DESCRIPTION
The ISSI IS61WV12816DAxx/DBxx and IS64WV12816DBxx
are high-speed, 2,097,152-bit static RAMs organized as
131,072 words by 16 bits. It is fabricated using ISSI's high-
performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques,
yields high-performance and low power consumption de-
vices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV12816DAxx/DBxx and IS64WV12816DBxx are
packaged in the JEDEC standard 44-pin TSOP Type II and
48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
JULY 2011
