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Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/21/2011
IS61WV12816DALL/DALS, IS61WV12816DBLL/DBLS,
IS64WV12816DBLL/DBLS
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-8 -10 -12
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 10 — 12 — ns
tSCE CE to Write End 6.5 — 8 — 9 — ns
tAW Address Setup Time 6.5 — 8 — 9 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWB LB, UB Valid to End of Write 6.5 — 8 — 9 — ns
tPWE1 WE Pulse Width 6.5 — 8 — 9 — ns
tPWE2 WE Pulse Width (OE = LOW) 8.0 — 10 — 11 — ns
tSD Data Setup to Write End 5 — 6 — 9 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 3.5 — 5 — 6 ns
tLZWE
(2)
WE HIGH to Low-Z Output 2 — 2 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write. Shaded area product in development
