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ADM1073ARU-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Data Sheet ADM1073
Rev. B | Page 3 of 24
GENERAL DESCRIPTION
(continued from Page 1)
Further control of the inrush current is provided by modulating
the width of the pulses, depending on the drain-source voltage
across the FET. This allows maximum charge transfer to the
load capacitance while maintaining the FET in its safe operating
area (SOA).
The default duty cycle of the pulse train is 6%, decreasing to
2.5% with maximum FET drain-source voltage, with a
maximum of seven successive autorestarts. After seven
successive autorestarts, the fault is latched and the part goes into
shutdown, with the result that the external FET is disabled until
the power is reset. The
LATCHED
output signal indicates when
the seven retries are complete.
Further programmability is offered by allowing alteration of the
default 6% ratio. An extra resistor between the TIMER pin and
V
EE
allows the ratio of on-time to off-time to be decreased,
while a resistor between TIMER and V
IN
allows the ratio to be
increased.
The ADM1073 has separate UV and OV pins for undervoltage
and overvoltage detection. The FET is turned off, if a
nontransient voltage less than the undervoltage threshold
(typically −36 V) is detected on the UV pin, or if greater than
the overvoltage threshold (typically −80 V) is detected on the
OV pin. The operating voltage window of the ADM1073 is
programmable via resistor networks on the UV and OV pins.
The hysteresis levels on the undervoltage and overvoltage
detectors can also be altered (see the Undervoltage/Overvoltage
Detection section). The
SPLYGD
output signal indicates when
the backplane supply is within the externally programmable
operating voltage range.
Other functions include
•
PWRGD
output, which can be used to enable a power
module (the DRAIN pin is monitored to determine when
the load capacitance is fully charged)
•
SHDN
input to manually disable the GATE drive
•
RESTART
input to remotely initiate a 5 second shutdown
The ADM1073 is fabricated using BiCMOS technology for
minimal power consumption and is available in a 14-lead
TSSOP package.
ADM1073 Data Sheet
Rev. B | Page 4 of 24
SPECIFICATIONS
V
DD
= 0 V, V
EE
= −48 V; T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions
BOARD SUPPLY (Not Connected Directly to Device) Limited by external components
Maximum Voltage Range −200 −48 −18 V
Typical Operating Voltage Range −80 −48 −35 V
V
IN
PIN—SHUNT REGULATOR
Operating Supply Voltage Range 11.7 12.3 12.9 V I
IN
= 0.6 mA to 2 mA
Quiescent Supply Current 300 500 μA V
IN
= 11.7 V
Maximum Shunt Supply Voltage 14 V I
IN
= 10 mA
Undervoltage Lockout, V
LKO
8 V
Power-On Reset Delay 150 ms
UV, OV PINS—UNDERVOLTAGE AND OVERVOLTAGE DETECTION
Undervoltage Falling Threshold, V
UVF
825 868 910 mV
Undervoltage Hysteresis Current 5 μA
Undervoltage Fault Filter 0.6 ms
Overvoltage Rising Threshold, V
OVR
1.86 1.93 2.00 V
Overvoltage Hysteresis Current 5 μA
Overvoltage Fault Filter 5 μs
Input Current 0.2 μA
GATE PIN—FET DRIVER
Maximum Gate Voltage 11.5 V
IN(MAX)
V I
GATE
= −1.0 μA
Minimum Gate Voltage 10 100 mV I
GATE
= 1.0 μA
Pull-Up Current −50 μA V
GATE
= 0 V to 8 V; V
SS
= 2 V
−36 μA V
GATE
= 0 V to 8 V; V
SS
= 0 V
Pull-Down Current 20 mA V
GATE
> 2 V
50 mA V
GATE
> 5 V
SENSE PIN—CURRENT SENSE—SOFT START
Current Limit Control Loop Threshold, V
ACL
97 100 103 mV I
GATE
= 0 mA
Circuit Breaker Limit Voltage, V
CB
86 90 mV
Fast Current Limit Voltage, V
FCL
110 mV
Control Loop Transconductance 4.5 μA/mV
Soft Start Pin Current 5 μA
TIMER PIN—PWM CONTROL
Minimum TIMER Pull-Up Current 18 19 20 μA I
PWRGD
< 4 μA; T
A
= 25°C to 85°C
16 19 20 μA I
PWRGD
< 4 μA
Maximum TIMER Pull-Up Current 37 39 41 μA I
PWRGD
= 24 μA; T
A
= 25°C to 85°C
34 39 41 μA I
PWRGD
= 24 μA
TIMER Pull-Down Current 1 μA
TIMER Low Voltage Trip Point 0.45 0.50 0.55 V
TIMER High Voltage Trip Point 2.34 2.42 2.50 V
Current Limit On-Time, t
ON
6 ms I
DRAIN
= 4 μA; C
TIMER
= 47 nF
Current Limit On-Time, t
ON
, with Foldback 3 ms I
DRAIN
= 20 μA; C
TIMER
= 47 nF
Number of Consecutive PWM Retry Cycles 7
Continuous Short-Circuit Time before Latched Shutdown 0.6 s C
TIMER
= 47 nF
Data Sheet ADM1073
Rev. B | Page 5 of 24
Parameter Min Typ Max Unit Test Conditions
DRAIN (FOLDBACK) AND
PWRGD
DRAIN Voltage at Which
PWRGD
Asserts 1.9 2 2.1 V R
DRAIN
= 3.75 M to 20 M
Maximum DRAIN Pin Current Allowable, I
DRAIN(MAX)
36 µA V
DS
= 80 V; R
DRAIN
= 3.25 M
PWRGD
Output Voltage Low 1 2 V
I
PWRGD
= 2.5 mA
0.2 0.4 V
I
PWRGD
= 0.5 mA
PWRGD
Internal Pull-Up Current 6 µA
PWRGD
Output Voltage High V
IN
V
RESTART
Time before Restart 5 s
Input Threshold 1.35 1.45 1.55 V
Glitch Filter 5 µs
Internal Pull-Up Current 6 µA
SHDN
Glitch Filter 5 µs
Input Threshold 1.35 1.45 1.55 V
Internal Pull-Up Current
6
µA
LATCHED
AND
SPLYGD
Output Voltage Low 1 2 V
I
LATCHED
, I
SPLYGD
= 2.5 mA
0.2 0.4 V
I
LATCHED
, I
SPLYGD
= 0.5 mA
Internal Pull-Up Current 6 µA
Output Voltage High V
IN
V
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADM1073ARU-REEL

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Manufacturer:
Analog Devices Inc.
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Hot Swap Voltage Controllers Full Featured -48V Hot Swap Ctrl'r I.C.
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