PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 10 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.2 Output Enable function (OE_N)
When input OE_N is asserted (active LOW), the IN_Dx and OUT_Dx signals are fully
functional. Input termination resistors are enabled and the internal bias circuits are turned
on.
When OE_N is de-asserted (inactive HIGH), the OUT_Dx outputs are in a
high-impedance state and drive zero output current. The IN_Dx input buffers are disabled
and IN_Dx termination is disabled. Power consumption is minimized.
Remark: Note that OE_N signal level has no influence on the HPD_SINK input,
HPD_SOURCE output, or the SCL and SDA level shifters. A transition from HIGH to LOW
at OE_N may disable the DDC channel for up to 20 s.
7.1.3 DDC channel enable function (DDC_EN)
The DDC_EN pin is active HIGH and can be used to isolate a badly behaved slave. When
DDC_EN is LOW, the DDC channel is turned off. The DDC_EN input should never
change state during an I
2
C-bus operation. Note that disabling DDC_EN during a bus
operation may hang the bus, while enabling DDC_EN during bus traffic would corrupt the
I
2
C-bus operation. Hence, DDC_EN should only be toggled while the bus is idle. (See
I
2
C-bus specification).
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 11 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.1.4 Enable/disable truth table
[1] A HIGH level on input OE_N disables only the TMDS channels. A transition from HIGH to LOW at OE_N may disable the DDC channel
for up to 20 s.
[2] A LOW level on input DDC_EN disables only the DDC channel.
[3] OUT_Dx channels ‘enabled’ means outputs OUT_Dx toggling in accordance with IN_Dx differential input voltage switching.
[4] DDC channel ‘enabled’ means SDA_SINK is connected to SDA_SOURCE and SCL_SINK is connected to SCL_SOURCE.
[5] The HPD_SOURCE output logic state always follows the HPD_SINK input logic state.
Table 3. HPD_SINK, OE_N and DDC_EN enabling truth table
Inputs Channels Mode
HPD_SINK OE_N
[1]
DDC_EN
[2]
IN_Dx OUT_Dx
[3]
DDC
[4]
HPD_SOURCE
[5]
LOW LOW LOW 50 termination
to V
RX(bias)
enabled high-impedance LOW Active; DDC
disabled
LOW LOW HIGH 50 termination
to V
RX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Active; DDC
enabled
LOW HIGH LOW high-impedance high-impedance;
zero output current
high-impedance LOW Standby
LOW HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
LOW Standby;
DDC
enabled
HIGH LOW LOW 50 termination
to V
RX(bias)
enabled high-impedance HIGH Active; DDC
disabled
HIGH LOW HIGH 50 termination
to V
RX(bias)
enabled SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Active; DDC
enabled
HIGH HIGH LOW high-impedance high-impedance;
zero output current
high-impedance HIGH Standby
HIGH HIGH HIGH high-impedance high-impedance;
zero output current
SDA_SINK
connected to
SDA_SOURCE
and SCL_SINK
connected to
SCL_SOURCE
HIGH Standby;
DDC
enabled
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 12 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7.2 Analog current reference
The REXT pin (pin 6) is an analog current sense port used to provide an accurate current
reference for the differential outputs OUT_Dx. For best output voltage swing accuracy,
use of a 10 k resistor (1 % tolerance) connected between this terminal and GND is
recommended.
If an external 10 k1 % resistor is not used, this pin can be connected to GND or V
DD
directly (0 ). In any of these cases, the output will function normally but at reduced
accuracy over voltage and temperature of the following parameters: output levels (V
OL
),
differential output voltage swing, and rise and fall time accuracy.
7.3 Equalizer
The PTN3360D supports 5 level equalization setting by the quinary input pin EQ5.
7.4 Backdrive current protection
The PTN3360D is designed for backdrive prevention on all sink-side TMDS outputs,
sink-side DDC I/Os and the HPD_SINK input. This supports user scenarios where the
display is connected and powered, but the PTN3360D is unpowered. In these cases, the
PTN3360D will sink no more than a negligible amount of leakage current, and will block
the display (sink) termination network from driving the power supply of the PTN3360D or
that of the inactive DVI or HDMI source.
7.5 Active DDC buffer with rise time accelerator
The PTN3360D DDC channel, besides providing 3.3 V to 5 V level shifting, includes
active buffering and rise time acceleration which allows up to 18 meters bus extension for
reliable DDC applications. While retaining all the operating modes and features of the
I
2
C-bus system during the level shifts, it permits extension of the I
2
C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) line as well as the
rise time accelerator on the sink-side port (SCL_SINK and SDA_SINK) enabling the bus
to drive a load up to 1400 pF or distance of 18 m on the sink-side port, and 400 pF on the
source-side port (SCL_SOURCE and SCA_SOURCE). Using the PTN3360D for DVI or
HDMI level shifting enables the system designer to isolate bus capacitance to
meet/exceed HDMI DDC specification. The SDA and SCL pins are overvoltage tolerant
and are high-impedance when the PTN3360D is unpowered or when DDC_EN is LOW.
Table 4. Equalizer settings
Inputs Quinary notation Equalizer mode
EQ5
short to GND 0
5
0dB
10 k resistor to GND 1
5
2dB
open-circuit 2
5
3.5 dB
10 k resistor to V
DD
3
5
9dB
short to V
DD
4
5
7dB

PTN3360DBS,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized High-speed level shifter
Lifecycle:
New from this manufacturer.
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