PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 4 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Topside mark Package
Name Description Version
PTN3360DBS PTN3360DBS HVQFN48 plastic thermal enhanced very thin quad flat package;
no leads; 48 terminals; body 7 7 0.85 mm
SOT619-1
Fig 2. Functional diagram of PTN3360D
002aaf241
OUT_D1
OUT_D1+
input bias
50 Ω50 Ω
IN_D1
IN_D1+
HPD level shifter
HPD_SOURCE
(0 V to 3.3 V)
HPD_SINK
(0 V to 5 V)
200 kΩ
SCL_SINK
SDA_SINK
DDC_EN (0 V to 3.3 V)
SCL_SOURCE
SDA_SOURCE
OUT_D2
OUT_D2+
IN_D2
IN_D2+
OUT_D3
OUT_D3+
IN_D3
IN_D3+
OUT_D4
OUT_D4+
IN_D4
IN_D4+
PTN3360D
OE_N
enable
enable
enable
enable
input bias
50 Ω50 Ω
input bias
50 Ω50 Ω
input bias
50 Ω50 Ω
enable
enable
enable
enable
DDC BUFFER
AND
LEVEL SHIFTER
EQ
EQ5
EQ
EQ
EQ
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 5 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
6. Pinning information
6.1 Pinning
HVQFN48 package supply ground is connected to both GND pins and exposed center pad.
GND pins and the exposed center pad must be connected to supply ground for proper device
operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs
to be soldered to the board using a corresponding thermal pad on the board and for proper heat
conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad
region.
Fig 3. Pin configuration for HVQFN48
OUT_D4+
OUT_D4
V
DD
OUT_D3+
OUT_D3
GND
OUT_D2+
OUT_D2
V
DD
OUT_D1+
OUT_D1
GND
OE_N
V
DD
GND
SCL_SINK
SDA_SINK
HPD_SINK
GND
DDC_EN
V
DD
n.c.
n.c.
GND
V
DD
GND
n.c.
SCL_SOURCE
SDA_SOURCE
HPD_SOURCE
REXT
GND
n.c.
EQ5
V
DD
GND
IN_D4+
IN_D4
V
DD
IN_D3+
IN_D3
GND
IN_D2+
IN_D2
V
DD
IN_D1+
IN_D1
GND
002aaf242
PTN3360DBS
12 25
11 26
10 27
9 28
8 29
7 30
6 31
5 32
4 33
3 34
2 35
1 36
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
terminal 1
index area
Transparent top view
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 6 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
6.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
OE_N, IN_Dx and OUT_Dx signals
OE_N 25 3.3 V low-voltage
CMOS single-ended
input
Output Enable and power saving function for
high-speed differential level shifter path.
When OE_N = HIGH:
IN_Dx termination = high-impedance
OUT_Dx outputs = high-impedance; zero
output current
When OE_N = LOW:
IN_Dx termination = 50
OUT_Dx outputs = active
IN_D4+ 48 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D4+ makes a differential pair with IN_D4.
The input to this pin must be AC coupled
externally.
IN_D4 47 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D4 makes a differential pair with IN_D4+.
The input to this pin must be AC coupled
externally.
IN_D3+ 45 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D3+ makes a differential pair with IN_D3.
The input to this pin must be AC coupled
externally.
IN_D3 44 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D3 makes a differential pair with IN_D3+.
The input to this pin must be AC coupled
externally.
IN_D2+ 42 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D2+ makes a differential pair with IN_D2.
The input to this pin must be AC coupled
externally.
IN_D2 41 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D2 makes a differential pair with IN_D2+.
The input to this pin must be AC coupled
externally.
IN_D1+ 39 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D1+ makes a differential pair with IN_D1.
The input to this pin must be AC coupled
externally.

PTN3360DBS,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized High-speed level shifter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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