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PTN3360DBS,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 7 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
IN_D1 38 Self-biasing
differential input
Low-swing differential input from display source
with PCI Express electrical signaling.
IN_D1 makes a differential pair with IN_D1+.
The input to this pin must be AC coupled
externally.
OUT_D4+ 13 TMDS differential
output
HDMI compliant TMDS output. OUT_D4+ makes
a differential pair with OUT_D4. OUT_D4+ is in
phase with IN_D4+.
OUT_D4 14 TMDS differential
output
HDMI compliant TMDS output. OUT_D4 makes
a differential pair with OUT_D4+. OUT_D4 is in
phase with IN_D4.
OUT_D3+ 16 TMDS differential
output
HDMI compliant TMDS output. OUT_D3+ makes
a differential pair with OUT_D3. OUT_D3+ is in
phase with IN_D3+.
OUT_D3 17 TMDS differential
output
HDMI compliant TMDS output. OUT_D3 makes
a differential pair with OUT_D3+. OUT_D3 is in
phase with IN_D3.
OUT_D2+ 19 TMDS differential
output
HDMI compliant TMDS output. OUT_D2+ makes
a differential pair with OUT_D2. OUT_D2+ is in
phase with IN_D2+.
OUT_D2 20 TMDS differential
output
HDMI compliant TMDS output. OUT_D2 makes
a differential pair with OUT_D2+. OUT_D2 is in
phase with IN_D2.
OUT_D1+ 22 TMDS differential
output
HDMI compliant TMDS output. OUT_D1+ makes
a differential pair with OUT_D1. OUT_D1+ is in
phase with IN_D1+.
OUT_D1 23 TMDS differential
output
HDMI compliant TMDS output. OUT_D1 makes
a differential pair with OUT_D1+. OUT_D1 is in
phase with IN_D1.
HPD and DDC signals
HPD_SINK 30 5 V CMOS
single-ended input
0 V to 5 V (nominal) input signal. This signal
comes from the DVI or HDMI sink. A HIGH value
indicates that the sink is connected; a LOW value
indicates that the sink is disconnected.
HPD_SINK is pulled down by an integrated
200 k
pull-down resistor.
HPD_
SOURCE 7 3.3 V CMOS
single-ended output
0 V to 3.3 V (nominal) output signal. This is
level-shifted version of the HPD_SINK signal.
SCL_SOURCE 9 single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC clock I/O. Pulled up by
external termination to 3.3 V. 5 V tolerant I/O.
SDA_SOURCE 8 single-ended 3.3 V
open-drain DDC I/O
3.3 V source-side DDC data I/O. Pulled up by
external termination to 3.3 V. 5 V tolerant I/O.
SCL_SINK 28 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC clock I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
SDA_SINK 29 single-ended 5 V
open-drain DDC I/O
5 V sink-side DDC data I/O. Pulled up by
external termination to 5 V. Provides rise time
acceleration for LOW-to-HIGH transitions.
Table 2. Pin description
…continued
Symbol Pin Type Description
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 8 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
[1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins and
the exposed center pad must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter.
When DDC_EN = LOW, buffer/level shifter is
disabled.
When DDC_EN = HIGH, buffer and level shifter
are enabled.
Supply and ground
V
DD
2, 11,
15, 21,
26, 33,
40, 46
3.3 V DC supply Supply voltage; 3.3 V 10 %.
GND
[1]
1, 5,
12, 18,
24, 27,
31, 36,
37, 43
ground Supply ground. All GND pins must be connected
to ground for proper operation.
Feature control signals
REXT 6 analog I/O Current sense port used to provide an accurate
current reference for the differential outputs
OUT_Dx. For best output voltage swing
accuracy, use of a 10 k resistor (1 % tolerance)
from this terminal to GND is recommended. May
also be tied to either V
DD
or GND directly (0 ).
See Section 7.2 for details.
n.c. 4, 10,
34, 35
- not connected
EQ5 3 3.3 V low-voltage
CMOS quinary input
Equalizer setting input pin. This pin can be
board-strapped to one of five decode values:
short to GND, resistor to GND, open-circuit,
resistor to V
DD
, short to V
DD
. See Table 4 for
truth table.
Table 2. Pin description …continued
Symbol Pin Type Description
PTN3360D All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 29 June 2012 9 of 24
NXP Semiconductors
PTN3360D
HDMI/DVI level shifter supporting 3 Gbit/s operation
7. Functional description
Refer to Figure 2 “Functional diagram of PTN3360D”.
The PTN3360D level shifts four lanes of low-swing AC-coupled differential input signals to
DVI and HDMI compliant open-drain current-steering differential output signals, up to
3.0 Gbit/s per lane to support 36-bit deep color mode. It has integrated 50 termination
resistors for AC-coupled differential input signals. An enable signal OE_N can be used to
turn off the TMDS inputs and outputs, thereby minimizing power consumption. The TMDS
outputs are back-power safe to disallow current flow from a powered sink while the
PTN3360D is unpowered.
The PTN3360D's DDC channel provides active level shifting and buffering, allowing 3.3 V
source-side termination and 5 V sink-side termination. The sink-side DDC ports are
equipped with a rise time accelerator enabling drive of long cables or high bus
capacitance. This enables the system designer to isolate bus capacitance to meet/exceed
HDMI DDC specification. The PTN3360D offers back-power safe sink-side I/Os to
disallow backdrive current from the DDC clock and data lines when power is off or when
DDC is not enabled. An enable signal DCC_EN enables the DDC level shifter block.
The PTN3360D also provides voltage translation for the Hot Plug Detect (HPD) signal
from 0 V to 5 V on the sink side to 0 V to 3.3 V on the source side.
The PTN3360D does not re-time any data. It contains no state machines. No inputs or
outputs of the device are latched or clocked. Because the PTN3360D acts as a
transparent level shifter, no reset is required.
7.1 Enable and disable features
PTN3360D offers different ways to enable or disable functionality, using the Output
Enable (OE_N), and DDC Enable (DDC_EN) inputs. Whenever the PTN3360D is
disabled, the device will be in Standby mode and power consumption will be minimal;
otherwise the PTN3360D will be in active mode and power consumption will be nominal.
These two inputs each affect the operation of PTN3360D differently: OE_N controls the
TMDS channels, DDC_EN affects only the DDC channel, and HPD_SINK does not affect
either of the channels. The following sections and truth table describe their detailed
operation.
7.1.1 Hot plug detect
The HPD channel of PTN3360D functions as a level-shifting buffer to pass the HPD logic
signal from the display sink device (via input HPD_SINK) on to the display source device
(via output HPD_SOURCE).
The output logic state of HPD_SOURCE output always follows the logic state of input
HPD_SINK, regardless of whether the device is in Active mode or Standby mode.
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PTN3360DBS,518

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Manufacturer:
NXP Semiconductors
Description:
Interface - Specialized High-speed level shifter
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