LTC3727A-1
10
3727a1fa
Main Control Loop
The LTC3727A-1 uses a constant frequency, current
mode step-down architecture with the two controller
channels operating 180 degrees out of phase. During
normal operation, each top MOSFET is turned on when
the clock for that channel sets the RS latch, and turned
off when the main current comparator, I
1
, resets the RS
latch. The peak inductor current at which I
1
resets the RS
latch is controlled by the voltage on the I
TH
pin, which is
the output of each error amplifi er EA. The V
OSENSE
pin
receives the voltage feedback signal, which is compared
to the internal reference voltage by the EA. When the load
current increases, it causes a slight decrease in V
OSENSE
relative to the 0.8V reference, which in turn causes the
I
TH
voltage to increase until the average inductor current
matches the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either the
inductor current starts to reverse, as indicated by current
comparator I
2
, or the beginning of the next cycle.
The top MOSFET drivers are biased from fl oating bootstrap
capacitor C
B
, which normally is recharged during each off
cycle through an external diode when the top MOSFET
turns off. As V
IN
decreases to a voltage close to V
OUT
,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about 400ns every
tenth cycle to allow C
B
to recharge.
The main control loop is shut down by pulling the
RUN/SS pin low. Releasing RUN/SS allows an internal
1.2μA current source to charge soft-start capacitor C
SS
.
When C
SS
reaches 1.5V, the main control loop is enabled
with the I
TH
voltage clamped at approximately 30% of its
maximum value. As C
SS
continues to charge, the I
TH
pin
voltage is gradually released allowing normal, full-current
operation. When both RUN/SS1 and RUN/SS2 are low, all
LTC3727A-1 controller functions are shut down, including
the 7.5V and 3.3V regulators.
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions: 1) to provide regulation for a secondary winding
by temporarily forcing continuous PWM operation on
both controllers; and 2) to select between two modes of
low current operation. When the FCB pin voltage is below
0.8V, the controller forces continuous PWM current mode
operation. In this mode, the top and bottom MOSFETs are
alternately turned on to maintain the output voltage inde-
pendent of direction of inductor current. When the FCB pin
is below V
INTVCC
– 2V but greater than 0.8V, the controller
enters Burst Mode operation. Burst Mode operation sets
a minimum output current level before inhibiting the top
switch and turns off the synchronous MOSFET(s) when
the inductor current goes negative. This combination of
requirements will, at low currents, force the I
TH
pin below
a voltage threshold that will temporarily inhibit turn-on of
both output MOSFETs until the output voltage drops. There
is 60mV of hysteresis in the burst comparator B tied to
the I
TH
pin. This hysteresis produces output signals to the
MOSFETs that turn them on for several cycles, followed by
a variable “sleep” interval depending upon the load cur-
rent. The resultant output voltage ripple is held to a very
small value by having the hysteretic comparator follow
the error amplifi er gain block.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to
be synchronized to an external source via the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator that
operates over a 250kHz to 550kHz range corresponding
to a DC voltage input from 0V to 2.4V. When locked, the
PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal. When PLLIN is left
open, the PLLFLTR pin goes low, forcing the oscillator to
its minimum frequency.
OPERATION
(Refer to Functional Diagram)