LTC3727A-1
25
3727a1fa
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(ΔI
L
) = 0.02Ω(2A) = 40mV
P–P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3727A-1. These items are also illustrated graphically in
the layout diagram of Figure 10; Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase synchronous regulators operating in continuous
mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C
IN
? Do not attempt to split the input decoupling for
the two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined LTC3727A-1 signal ground pin and the ground
return of C
INTVCC
must return to the combined C
OUT
(–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to
the (–) terminals of the input capacitor by placing the
capacitors next to each other and away from the Schottky
loop described above.
3. Do the LTC3727A-1 V
OSENSE
pins resistive dividers con-
nect to the (+) terminals of C
OUT
? The resistive divider must
be connected between the (+) terminal of C
OUT
and signal
ground. The R2 and R4 connections should not be along
the high current input feeds from the input capacitor(s).
APPLICATIONS INFORMATION
4. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The fi lter capacitor between
SENSE
+
and SENSE
–
should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1μF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve noise
performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC3727A-1 and occupy minimum PC trace area.
7. Use a modifi ed “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output capaci-
tors with tie-ins for the bottom of the INTV
CC
decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope to
the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
