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USB2422T-I/MJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
USB2422
DS00001726B-page 16 2013 - 2015 Microchip Technology Inc.
4.0 CONFIGURATION OPTIONS
Microchip’s USB 2.0 hub is fully compliant with the USB Specification [1]. Refer to Chapter 10 (Hub Specification) for
general details regarding hub operation and functionality.
The hub provides one Transaction Translator (TT) that is shared by both downstream ports (defined as Single-TT con-
figuration). The TT contains 4 non-periodic buffers.
4.1 Hub Configuration
The USB2422 only supports internal defaults with the exception of the non-removable strap option (using
NON_REM[1:0]). The hub internal default settings are as follows:
• Internal Default Configuration without over-rides
• Strap options enabled
• Self-powered operation enabled
• Individual power switching
• Individual over-current sensing
4.2 Resets
There are two device resets: a hardware reset via RESET_N, and a USB Bus Reset.
4.2.1 EXTERNAL HARDWARE RESET_N
A valid hardware reset is defined as assertion of RESET_N for a minimum of 1 μs after all power supplies are within
operating range. While reset is asserted, the hub (and its associated external circuitry) consumes less than 500 μA of
current from the upstream USB power source.
Assertion of RESET_N causes the following:
1. All downstream ports are disabled.
2. The PRTPWR power to downstream devices is turned on when battery charging is enabled for a specific port,
and removed when battery charging is disabled for a specific port.
3. The PHYs are disabled, and the differential pairs will be in a high-impedance state.
4. All transactions immediately terminate; no states are saved.
5. All internal registers return to the default state (in most cases, 00h).
6. The external crystal oscillator is halted.
7. The PLL is halted.
TABLE 4-1: HUB CONFIGURATION OPTIONS
CFG_SEL Description
0 Default configuration:
• Strap options enabled
• Hub descriptors indicate the hub as “self-powered”
1 The hub is configured externally over SMBus (as an SMBus slave
device with address 0101100b):
• Strap options disabled
• Self-powered or bus-powered depending on register settings
• All registers configured over SMBus
2013 - 2015 Microchip Technology Inc. DS00001726B-page 17
USB2422
4.2.1.1 Hub Configuration Timing for Strapping Option
4.2.2 USB BUS RESET
In response to the upstream port signaling a reset to the hub, the hub does the following:
1. Sets default address to 0.
2. Sets configuration to unconfigured.
3. The PRTPWR power to downstream devices is turned on when battery charging is enabled for a specific port,
and removed when battery charging is disabled for a specific port.
4. Clears all TT buffers.
5. Moves device from suspended to active (if suspended).
6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence.
The host then configures the hub and the hub’s downstream port devices in accordance with the specification.
The hub does not propagate the upstream USB reset to downstream devices.
FIGURE 4-1: HUB CONFIGURATION TIMING
TABLE 4-2: HUB CONFIGURATION TIMING
Name Description MIN TYP MAX Units
t1 RESET_N asserted 1 μsec
t2 Strap setup time 16.7 nsec
t3 Strap hold time 16.7 1400 nsec
t4 Hub outputs driven to inactive logic states 1.5 2 μsec
t5 USB attach (See Note) 3 μsec
t6 Host acknowledges attach and signals USB reset 100 msec
t7 USB idle undefined msec
t8 Completion time for requests (with or without data
stage)
5 msec
Note: All power supplies must have reached the operating levels mandated in Section 5.0, "DC Parameters",
prior to (or coincident with) the assertion of RESET_N.
t1
t4
t5
t6
t7 t8
Valid Driven by Hub if strap is an output
RESET_N
VSS
NON_REM[1:0]
VSS
Hardware
reset asserted
Read
NON_REM[1:0]
Drive Strap
Outputs to
inactive levels
Attach
USB
Upstream
Attach
Debounce
Interval Idle
Start completion
request response
t2
t3
Don’t Care
Don’t Care
USB2422
DS00001726B-page 18 2013 - 2015 Microchip Technology Inc.
4.3 SMBus
The Microchip hub can be configured by an external processor via an SMBus interface (see Table 4-1 for details on
enabling the SMBus interface). The Microchip hub waits indefinitely for the SMBus code load to complete and only
appears as a newly connected device on USB after the code load is complete.
The hub’s SMBus acts as a slave-only SMBus device. The implementation only supports block write (Section 4.3.2.1)
and block read (Section 4.3.2.2) protocols. Reference the System Management Bus Specification [2] for additional infor-
mation.
Refer to Section 4.4, "SMBus Registers," on page 20 for details on all SMBus accessible registers.
4.3.1 SMBUS SLAVE ADDRESS
The 7-bit slave address is 0101100b. The hub will not respond to the general call address of 0000000b.
4.3.2 PROTOCOL IMPLEMENTATION
Typical block write and block read protocols are shown in figures 4-2 and 4-3. Register accesses are performed using
7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading shown in the figures during a
read or write indicates the hub is driving data on the SMBDATA line; otherwise, host data is on the SMBDATA line.
The SMBus slave address assigned to the hub (0101100b) allows it to be identified on the SMBus. The register address
field is the internal address of the register to be accessed. The register data field is the data that the host is attempting
to write to the register or the contents of the register that the host is attempting to read.
4.3.2.1 Block Write/Read
The block write begins with a slave address and a write condition. After the command code, the host issues a byte count
which describes how many more bytes will follow in the message. If a slave had 20 bytes to send, the first byte would
be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be zero. A block write or read allows
a transfer maximum of 32 data bytes.
Note: Data bytes are transferred MSB first.
Note: For the following SMBus tables:
FIGURE 4-2: BLOCK WRITE
Denotes Master-to-Slave Denotes Slave-to-Master
S Slave Address Register AddressWr A
17118
A
1
...
181
Byte Count = N
A Data byte 1 A Data byte 2 A
81 1 188
Data byte N A P
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

USB2422T-I/MJ

Mfr. #:
Buy USB2422T-I/MJ
Manufacturer:
Microchip Technology
Description:
USB Interface IC Low Pin Count 2-Port USB 2.0 Hi-Speed Hub Controller
Lifecycle:
New from this manufacturer.
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