OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

USB2422T-I/MJ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47
2013 - 2015 Microchip Technology Inc. DS00001726B-page 19
USB2422
4.3.2.2 Block Read
A block read differs from a block write in that the repeated start condition exists to satisfy the SMBus specification’s
requirement for a change in the transfer direction.
4.3.2.3 Invalid Protocol Response Behavior
Note that any attempt to update registers with an invalid protocol will not be updated. The only valid protocols are write
block and read block (described above), where the hub only responds to the 7-bit hardware selected slave address
(0101100b).
4.3.3 SLAVE DEVICE TIMEOUT
Devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds
25 ms (T
TIMEOUT, MIN
). The master must detect this condition and generate a stop condition within or after the transfer
of the interrupted data byte. Slave devices must reset their communication and be able to receive a new START condi-
tion no later than 35 ms (T
TIMEOUT, MAX
).
4.3.4 STRETCHING THE SCLK SIGNAL
The hub supports stretching of the SCLK by other devices on the SMBus. However, the hub does not stretch the SCLK.
4.3.5 SMBUS TIMING
The SMBus slave interface complies with the SMBus Specification Revision 1.0 2.. See Section 2.1, AC Specifications
on page 3 for more information.
4.3.6 BUS RESET SEQUENCE
The SMBus slave interface resets and returns to the idle state upon a START condition followed immediately by a STOP
condition.
4.3.7 SMBUS ALERT RESPONSE ADDRESS
The SMBALERT# signal is not supported by the hub.
FIGURE 4-3: BLOCK READ
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its
communications port after a start or stop condition. The slave device timeout must be implemented.
1
SS Slave Address Register AddressWr
1711 8
A
1
Slave Address Rd A
711
...
A
81 1 188 181
PA AAAByte Count = N Data byte 2Data byte 1 Data byte N
USB2422
DS00001726B-page 20 2013 - 2015 Microchip Technology Inc.
4.4 SMBus Registers
This section details the device SMBus registers.
Note: Internal Default ROM values are not visible to THE SMBus interface and cannot be read. When the hub is
configured for SMBus register load, the entire register set must be written.
TABLE 4-3: INTERNAL DEFAULT AND SMBUS REGISTER MEMORY MAP
Reg.
Address
Type Register Name
Internal
Default
ROM
SMBus &
EEPROM
Default
00h R/W Vendor ID Least Significant Bit Register (VIDL) 24h 00h
01h R/W Vendor ID Most Significant Bit Register (VIDM) 04h 00h
02h R/W Product ID Least Significant Bit Register (PIDL) 22h 00h
03h R/W Product ID Most Significant Bit Register (PIDM) 24h 00h
04h R/W Device ID Least Significant Bit Register (DIDL) A0h 00h
05h R/W Device ID Most Significant Bit Register (DIDM) 00h 00h
06h R/W Configuration Data Byte 1 Register (CFG1) 8Bh 00h
07h R/W Configuration Data Byte 2 Register (CFG2) 20h 00h
08h R/W Configuration Data Byte 3 Register (CFG3) 02h 00h
09h R/W Non-Removable Device Register (NRD) 00h 00h
0Ah R/W Port Disable for Self-Powered Operation Register (PDS) 00h 00h
0Bh R/W Port Disable for Bus-Powered Operation Register (PDB) 00h 00h
0Ch R/W Max Power for Self-Powered Operation Register (MAXPS) 01h 00h
0Dh R/W Max Power for Bus-Powered Operation Register (MAXPB) 32h 00h
0Eh R/W Hub Controller Max Current for Self-Powered Operation Register
(HCMCS)
01h 00h
0Fh R/W Hub Controller Max Power for Bus-Powered Operation Register
(HCMCB)
32h 00h
10h R/W Power-On Time Register (PWRT) 32h 00h
11h R/W Language ID High Register (LANGIDH) 00h 00h
12h R/W Language ID Low Register (LANGIDL) 00h 00h
13h R/W Manufacturer String Length Register (MFRSL) 00h 00h
14h R/W Product String Length Register (PRDSL) 00h 00h
15h R/W Serial String Length Register (SERSL) 00h 00h
16h-53h R/W Manufacturer String Registers (MANSTR) 00h 00h
54h-91h R/W Product String Registers (PRDSTR) 00h 00h
92h-CFh R/W Serial String Registers (SERSTR) 00h 00h
D0h R/W Battery Charging Enable Register (BC_EN) 00h 00h
E0h-F5h - RESERVED - -
F6h R/W Boost Upstream Register (BOOSTUP) 00h 00h
F7h - RESERVED - -
F8h R/W Boost Downstream Register (BOOST40) 00h 00h
F9h - RESERVED - -
FAh R/W Port Swap Register (PRTSP) 00h 00h
FBh R/W Port 1/2 Remap Register (PRTR12) 00h 00h
FCh-FEh - RESERVED - -
FFh R/W Status/Command Register (STCD)
00h 00h
2013 - 2015 Microchip Technology Inc. DS00001726B-page 21
USB2422
4.4.1 VENDOR ID LEAST SIGNIFICANT BIT REGISTER (VIDL)
4.4.2 VENDOR ID MOST SIGNIFICANT BIT REGISTER (VIDM)
4.4.3 PRODUCT ID LEAST SIGNIFICANT BIT REGISTER (PIDL)
4.4.4 PRODUCT ID MOST SIGNIFICANT BIT REGISTER (PIDM)
Offset: 00h Size: 8 bits
Bits Description Type Default
7:0 Least Significant Byte of the Vendor ID (VID_LSB)
This is a 16-bit value that uniquely identifies the Vendor of the user device
(assigned by USB-Interface Forum). This field is set by the OEM using the
SMBus interface option.
R/W 00h
Address: 01h Size: 8 bits
Bits Description Type Default
7:0 Most Significant Byte of the Vendor ID (VID_LSB)
This is a 16-bit value that uniquely identifies the Vendor of the user device
(assigned by USB-Interface Forum). This field is set by the OEM using the
SMBus interface options.
R/W 00h
Address: 02h Size: 8 bits
Bits Description Type Default
7:0 Least Significant Byte of the Product ID (PID_LSB)
This is a 16-bit value that the Vendor can assign that uniquely identifies this
particular product (assigned by OEM). This field is set by the OEM using the
SMBus interface options.
R/W 00h
Address: 03h Size: 8 bits
Bits Description Type Default
7:0 Most Significant Byte of the Product ID (PID_LSB)
This is a 16-bit value that the Vendor can assign that uniquely identifies this
particular product (assigned by OEM). This field is set by the OEM using
either SMBus interface options.
R/W 00h
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P47

USB2422T-I/MJ

Mfr. #:
Buy USB2422T-I/MJ
Manufacturer:
Microchip Technology
Description:
USB Interface IC Low Pin Count 2-Port USB 2.0 Hi-Speed Hub Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet