LTM9002
25
9002f
APPLICATIONS INFORMATION
Data Format
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
Note that MODE controls both channel A and channel B.
Connecting MODE to GND or 1/3 V
DD
selects straight
binary output format. Connecting MODE to 2/3 V
DD
or
V
DD
selects 2’s complement output format. An external
resistive divider can be used to set the 1/3 V
DD
or 2/3
V
DD
logic values. Table 7 shows the logic states for the
MODE pin.
Table 7. MODE Pin Function
MODE PIN OUTPUT FORMAT
CLOCK DUTY CYCLE
STABILIZER
0 Straight Binary Off
1/3V
DD
Straight Binary On
2/3V
DD
2’s Complement On
V
DD
2’s Complement Off
Overfl ow Bit
For LTM9002-AA, when OF outputs a logic high the con-
verter is either overranged or underranged on channel A
or channel B. Note that both channels share a common
OF pin. OF is disabled when channel A is in sleep or nap
mode. For LTM9002-LA, OFA and OFB indicate either
condition for the respective channel.
Output Clock
The LTM9002-AA has a delayed version of the CLKB input
available as a digital output, CLKOUT. The falling edge of
the CLKOUT pin can be used to latch the digital output
data. CLKOUT is disabled when channel B is in sleep or
nap mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same supply that powers the logic being driven.
For example, if the converter drives a DSP powered by a
1.8V supply, then OV
DD
should be tied to that same 1.8V
supply.
OV
DD
can be powered with any voltage from 500mV up to
3.6V, independent of V
DD
. OGND can be powered with any
voltage from GND up to 1V and must be less than OV
DD
.
The logic outputs will swing between OGND and OV
DD
.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full-speed
operation. The output Hi-Z state is intended for use during
test or initialization. Channels A and B have independent
output enable pins (OEA, OEB.)
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting ADCSHDN to GND results
in normal operation. Connecting ADCSHDN to V
DD
and
OE to V
DD
results in sleep mode, which powers down all
circuitry including the reference and the ADC typically
dissipates 1mW. When exiting sleep mode, it will take
700μs to 1ms for the output data to become valid because
the reference capacitors have to recharge and stabilize.
Connecting ADCSHDN to V
DD
and OE to GND results in
nap mode and the ADC typically dissipates 30mW. In nap
mode, the on-chip reference circuit is kept on, so that
recovery from nap mode is faster than that from sleep
mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Channels A and B have independent ADCSHDN pins
(ADCSHDNA, ADCSHDNB.) Channel A is controlled by
ADCSHDNA and OEA, and channel B is controlled by
ADCSHDNB and OEB. The nap, sleep and output enable
modes of the two channels are completely independent,
so it is possible to have one channel operating while the
other channel is in nap or sleep mode.
Digital Output Multiplexer
The digital outputs of the ADC can be multiplexed onto a
single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is high, channel A comes
out on DAx; channel B comes out on DBx. If MUX is low,
LTM9002
26
9002f
APPLICATIONS INFORMATION
the output busses are swapped and channel A comes
out on DBx; channel B comes out on DAx. To multiplex
both channels onto a single output bus, connect MUX,
CLKA and CLKB together (see the Timing Diagram for
the multiplexed mode.) The multiplexed data is available
on either data bus – the unused data bus can be disabled
with its OE pin.
Supply Sequencing
The V
CC
pin provides the supply to the amplifi er and the
auxiliary DAC while the V
DD
pin provides the supply to the
ADC. The amplifi er, ADC and the DAC are separate integrated
circuits within the LTM9002; however, there are no supply
sequencing considerations beyond standard practice. It is
recommended that the amplifi er, ADC and DAC all use the
same low noise, 3.0V supply, but V
CC
may be operated from
a different voltage level if desired. Both rails can operate
from the same 3.0V linear regulator but place a ferrite bead
between the V
CC
and V
DD
pins. Separate linear regulators
can be used without additional supply sequencing circuitry
if they have common input supplies.
Grounding and Bypassing
The LTM9002 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9002 has been optimized for a fl ow-through layout
so that the interaction between inputs and digital outputs
is minimized. A continuous row of ground pads facilitate
a layout that ensures that digital and analog signal lines
are separated as much as possible.
The LTM9002 is internally bypassed with the ADC, (V
DD
) and
amplifi er and DAC (V
CC
) supplies returning to a common
ground (GND). The digital output supply (OV
DD
) is returned
to OGND. Additional bypass capacitance is optional and
may be required if power supply noise is signifi cant.
The differential inputs should run parallel and close to each
other. The input traces should be as short as possible to
minimize capacitance and to minimize noise pickup.
Heat Transfer
Most of the heat generated by the LTM9002 is transferred
through the bottom-side ground pads. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of suffi cient area with as
many vias as possible.
Recommended Layout
The high integration of the LTM9002 makes the PC board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
Use large PCB copper areas for ground. This helps
to dissipate heat in the package through the board
and also helps to shield sensitive on-board analog
signals. Common ground (GND) and output ground
(OGND) are electrically isolated on the LTM9002, but
can be connected on the PCB underneath the part to
provide a common return path.
Use multiple ground vias. Using as many vias as
possible helps to improve the thermal performance
of the board and creates necessary barriers separat-
ing analog and digital traces on the board at high
frequencies.
Separate analog and digital traces as much as pos-
sible, using vias to create high-frequency barriers.
This will reduce digital feedback that can reduce the
signal-to-noise ratio (SNR) and dynamic range of the
LTM9002.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
use a type 3 or 4 printing no-clean solder paste. The solder
stencil design should follow the guidelines outlined in
Application Note 100.
The LTM9002 employs gold-fi nished pads for use with
Pb-based or tin-based solder paste. It is inherently Pb-free
and complies with the JEDEC (e4) standard. The materi-
als declaration is available online at http://www.linear.
com/leadfree/mat_dec.jsp.
LTM9002
27
9002f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
LAND DESIGNATION PER JESD MO-222, SPP-010
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 108
4
3
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
SYMBOL
aaa
bbb
eee
TOLERANCE
0.15
0.10
0.05
2.22 – 2.42
DETAIL B
DETAIL B
SUBSTRATE
MOLD
CAP
0.27 – 0.37
1.95 – 2.05
Z
11.25
BSC
PACKAGE TOP VIEW
15
BSC
4
PAD 1
CORNER
X
Y
aaa Z
aaa Z
DETAIL A
10.16
BSC
1.27
BSC
13.97
BSC
11 10 9 8 7 6 5 4 3 2
PACKAGE BOTTOM VIEW
DIA (0.635)
PAD 1
3
PADS
SEE NOTES
12 1
A
B
C
D
E
F
G
H
J
SUGGESTED PCB LAYOUT
TOP VIEW
1.270
1.270
0.000
2.540
2.540
3.810
3.810
5.080
5.080
6.985
6.985
5.715
5.715
4.445
4.445
3.175
3.175
1.905
1.905
0.635
0.635
0.000
LGA 108 0707 REV Ø
PACKAGE IN TRAY LOADING ORIENTATION
LTMXXXXXX
μModule
TRAY PIN 1
BEVEL
COMPONENT
PIN “A1”
// bbb Z
0.22 × 45°
CHAMFER
DETAIL A
0.630 ±0.025 SQ. 108x
S
YXeee
LGA Package
108-Lead (15mm × 11.25mm × 2.32mm)
(Reference LTC DWG # 05-08-1757 Rev Ø)

LTM9002IV-LA#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 12-bit, Dual IF/Baseband Receiver Module, 65Msps, DC-25MHz LPF, 8dB/20dB gain, no trim DAC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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