21.The internal write time of the memory is defined by the overlap of WE = V
IL
, CE = V
IL
and BHE or BLE = V
IL
. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22.Data I/O is in high-impedance state if CE
= V
IH
, or OE = V
IH
or BHE, and/or BLE = V
IH
.
23.The minimum write cycle pulse width should be equal to sum of t
HZWE
and t
SD
.
24.During this period the I/Os are in output state. Do not apply input signals.
Document Number: 002-03314 Rev. *C Page 11 of 18
CY7C1051H
Figure 8. Write Cycle No. 3 (WE controlled)
[25, 26]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/BLE
DATA I/O
OE
t
WC
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
BW
t
HD
t
HZOE
t
SD
DATA
IN
VALID
Note27
Notes
25.The internal write time of the memory is defined by the overlap of WE = V
IL
, CE = V
IL
and BHE or BLE = V
IL
. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26.Data I/O is in high-impedance state if CE
= V
IH
, or OE = V
IH
or BHE, and/or BLE = V
IH
.
27.During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-03314 Rev. *C Page 12 of 18
CY7C1051H
Figure 9. Write Cycle No. 4 (BLE or BHE Controlled)
[28, 29]
Switching Waveforms (continued)
DATA
IN
VALID
ADDRESS
CE
WE
DATA I/O
t
WC
t
SCE
t
AW
t
SA
t
BW
t
HA
t
HD
t
HZWE
t
SD
BHE/
BLE
t
PWE
t
LZWE
Note 30
Notes
28.The internal write time of the memory is defined by the overlap of WE = V
IL
, CE = V
IL
, and BHE or BLE = V
IL
. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
29.Data I/O is in high-impedance state if CE
= V
IH
, or OE = V
IH
, or BHE, and/or BLE = V
IH
.
30.During this period, the I/Os are in output state. Do not apply input signals.
