Document Number: 002-03314 Rev. *C Page 8 of 18
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter
[10]
Description
10 ns
Unit
Min Max
Read Cycle
t
POWER
V
CC
(stable) to the first access
[11, 12]
100.0 – µs
t
RC
Read cycle time 10.0 – ns
t
AA
Address to data valid – 10.0 ns
t
OHA
Data hold from address change 3.0 – ns
t
ACE
CE LOW to data valid – 10.0 ns
t
DOE
OE LOW to data valid – 5.0 ns
t
LZOE
OE LOW to low Z
[13, 14, 15]
0–ns
t
HZOE
OE HIGH to high Z
[13, 14, 15]
–5.0ns
t
LZCE
CE LOW to low Z
13, 14, 15]
3.0 – ns
t
HZCE
CE HIGH to high Z
[13, 14, 15]
–5.0ns
t
PU
CE LOW to power-up
[12]
0–ns
t
PD
CE HIGH to power-down
[12]
–10.0ns
t
DBE
Byte enable to data valid – 5.0 ns
t
LZBE
Byte enable to low Z
[13, 14]
0–ns
t
HZBE
Byte disable to high Z
[13, 14]
–6.0ns
Write Cycle
[16, 17]
t
WC
Write cycle time 10.0 – ns
t
SCE
CE LOW to write end 7.0 – ns
t
AW
Address setup to write end 7.0 – ns
t
HA
Address hold from write end 0–ns
t
SA
Address setup to write start 0 – ns
t
PWE
WE pulse width 7.0 – ns
t
SD
Data setup to write end 5.0 – ns
t
HD
Data hold from write end 0 – ns
t
LZWE
WE HIGH to low Z
[13, 14, 15]
3.0 – ns
t
HZWE
WE LOW to high Z
[13, 14, 15]
–5.0ns
t
BW
Byte Enable to write end 7.0 – ns
Notes
10. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for V
CC
> 3 V) and V
CC
/2 (for V
CC
< 3 V), and input pulse levels
of 0 to 3 V (for V
CC
> 3 V) and 0 to V
CC
(for V
CC
< 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 2 on page 6, unless specified otherwise.
11. t
POWER
gives the minimum amount of time that the power supply is at stable V
CC
until the first memory access is performed.
12. These parameters are guaranteed by design and are not tested.
13. t
HZOE
, t
HZCE
, t
HZWE
, and t
HZBE
are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 2 on page 6. Hi-Z, Lo-Z transition is measured 200 mV from steady state
voltage.
14. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
15. Tested initially and after any design or process changes that may affect these parameters.
16. The internal write time of the memory is defined by the overlap of WE
= V
IL
, CE = V
IL
, and BHE or BLE = V
IL
. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
17. The minimum write pulse width for Write Cycle No. 2 (WE
Controlled, OE LOW) should be sum of t
HZWE
and t
SD
.
