Document Number: 002-03314 Rev. *C Page 13 of 18
CY7C1051H
Truth Table
CE OE WE BLE BHE I/O
0
–I/O
7
I/O
8
–I/O
15
Mode Power
HX
[31]
X
[31]
X
[31]
X
[31]
High-Z High-Z Power down Standby (I
SB
)
L L H L L Data out Data out Read all bits Active (I
CC
)
L L H L H Data out High-Z Read lower bits only Active (I
CC
)
L L H H L High-Z Data out Read upper bits only Active (I
CC
)
L X L L L Data in Data in Write all bits Active (I
CC
)
L X L L H Data in High-Z Write lower bits only Active (I
CC
)
L X L H L High-Z Data in Write upper bits only Active (I
CC
)
L H H X X High-Z High-Z Selected, outputs disabled Active (I
CC
)
L X X H H High-Z High-Z Selected, outputs disabled Active (I
CC
)
Note
31. The input voltage levels on these pins should be either at V
IH
or V
IL
.
Document Number: 002-03314 Rev. *C Page 14 of 18
CY7C1051H
Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range
Ordering Code
Package
Diagram
Package Type
(all Pb-free)
Key Features /
Differentiators
Operating
Range
10 2.2 V–3.6 V CY7C1051H30-10ZSXI 51-85087 44-pin TSOP II Single Chip Enable Industrial
CY7C1051H30-10ZSXIT
X = Blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type:
ZS = 44-pin TSOP II
Speed: 10 ns
Voltage Range:
30 = 2.2 V–3.6 V
Process Technology: Revision Code “H” = 65 nm Technology
Data Width: 1 = × 16-bits
Density: 05 = 8-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1
-
10
I7 05 G1
ZS
XX XX
Document Number: 002-03314 Rev. *C Page 15 of 18
CY7C1051H
Package Diagram
Figure 10. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E

CY7C1051H30-10ZSXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM Async SRAMS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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