7
82C54
The status register, shown in the figure, when latched,
contains the current contents of the Control Word Register
and status of the output and null count flag. (See detailed
explanation of the Read-Back command.)
The actual counter is labeled CE (for Counting Element). It is
a 16-bit presettable synchronous down counter.
OLM and OLL are two 8-bit latches. OL stands for “Output
Latch”; the subscripts M and L for “Most significant byte” and
“Least significant byte”, respectively. Both are normally referred
to as one unit and called just OL. These latches normally
“follow” the CE, but if a suitable Counter Latch Command is
sent to the 82C54, the latches “latch” the present count until
read by the CPU and then return to “following” the CE. One
latch at a time is enabled by the counter’s Control Logic to drive
the internal bus. This is how the 16-bit Counter communicates
over the 8-bit internal bus. Note that the CE itself cannot be
read; whenever you read the count, it is the OL that is being
read.
Similarly, there are two 8-bit registers called CRM and CRL (for
“Count Register”). Both are normally referred to as one unit and
called just CR. When a new count is written to the Counter, the
count is stored in the CR and later transferred to the CE. The
Control Logic allows one register at a time to be loaded from
the internal bus. Both bytes are transferred to the CE
simultaneously. CRM and CRL are cleared when the Counter is
programmed for one byte counts (either most significant byte
only or least significant byte only) the other byte will be zero.
Note that the CE cannot be written into; whenever a count is
written, it is written into the CR.
The Control Logic is also shown in the diagram. CLK n,
GATE n, and OUT n are all connected to the outside world
through the Control Logic.
82C54 System Interface
The 82C54 is treated by the system software as an array of
peripheral I/O ports; three are counters and the fourth is a
control register for MODE programming.
Basically, the select inputs A0, A1 connect to the A0, A1
address bus signals of the CPU. The CS
can be derived
directly from the address bus using a linear select method or
it can be connected to the output of a decoder.
Operational Description
General
After power-up, the state of the 82C54 is undefined. The
Mode, count value, and output of all Counters are undefined.
How each Counter operates is determined when it is
programmed. Each Counter must be programmed before it
can be used. Unused counters need not be programmed.
Programming the 82C54
Counters are programmed by writing a Control Word and
then an initial count.
All Control Words are written into the Control Word Register,
which is selected when A1, A0 = 11. The Control Word
specifies which Counter is being programmed.
By contrast, initial counts are written into the Counters, not
the Control Word Register. The A1, A0 inputs are used to
select the Counter to be written into. The format of the initial
count is determined by the Control Word used.
Write Operations
The programming procedure for the 82C54 is very flexible.
Only two conventions need to be remembered:
1. For Each Counter, the Control Word must be written
before the initial count is written.
2. The initial count must follow the count format specified in the
Control Word (least significant byte only, most significant
byte only, or least significant byte and then most significant
byte).
INTERNAL BUS
CONTROL
LOGIC
CONTROL
WORD
REGISTER
STATUS
LATCH
STATUS
REGISTER
CLK n
GATE n
OUT n
OL
M
OL
L
CE
CR
M
CR
L
FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
I/OR
I/OW
WR
RD
CS
A0
A1
A1 A0
8
COUNTER
0
OUTGATE CLK
COUNTER
1
COUNTER
2
OUTGATE CLK OUT GATE CLK
D0 - D7
82C54
FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAM
8
82C54
Since the Control Word Register and the three Counters have
separate addresses (selected by the A1, A0 inputs), and each
Control Word specifies the Counter it applies to (SC0, SC1
bits), no special instruction sequence is required. Any
programming sequence that follows the conventions above is
acceptable.
CONTROL WORD FORMAT
A1, A0 = 11; CS
= 0; RD = 1; WR = 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD
SC - SELECT COUNTER
SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read-Back Command (See Read Operations)
RW - READ/WRITE
RW1 RW0
0 0 Counter Latch Command (See Read Operations)
0 1 Read/Write least significant byte only.
1 0 Read/Write most significant byte only.
1 1 Read/Write least significant byte first, then most
significant byte.
M - MODE
M2 M1 M0
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
BCD - BINARY CODED DECIMAL
0 Binary Counter 16-bit
1 Binary Coded Decimal (BCD) Counter (4 Decades)
NOTE: Don’t Care bits (X) should be 0 to insure compatibility with
future products.
POSSIBLE PROGRAMMING SEQUENCE
A1 A0
Control Word - Counter 0 1 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 0 0 0
Control Word - Counter 1 1 1
LSB of Count - Counter 1 0 1
MSB of Count - Counter 1 0 1
Control Word - Counter 2 1 1
LSB of Count - Counter 2 1 0
MSB of Count - Counter 2 1 0
POSSIBLE PROGRAMMING SEQUENCE
A1 A0
Control Word - Counter 0 1 1
Control Word - Counter 1 1 1
Control Word - Counter 2 1 1
LSB of Count - Counter 2 1 0
LSB of Count - Counter 1 0 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 0 0 0
MSB of Count - Counter 1 0 1
MSB of Count - Counter 2 1 0
POSSIBLE PROGRAMMING SEQUENCE
A1 A0
Control Word - Counter 2 1 1
Control Word - Counter 1 1 1
Control Word - Counter 0 1 1
LSB of Count - Counter 2 1 0
MSB of Count - Counter 2 1 0
LSB of Count - Counter 1 0 1
MSB of Count - Counter 1 0 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 0 0 0
9
82C54
A new initial count may be written to a Counter at any time
without affecting the Counter’s programmed Mode in any way.
Counting will be affected as described in the Mode definitions.
The new count must follow the programmed count format.
If a Counter is programmed to read/write two-byte counts,
the following precaution applies. A program must not
transfer control between writing the first and second byte to
another routine which also writes into that same Counter.
Otherwise, the Counter will be loaded with an incorrect
count.
READ OPERATIONS
It is often desirable to read the value of a Counter without
disturbing the count in progress. This is easily done in the
82C54.
There are three possible methods for reading the Counters.
The first is through the Read-Back command, which is
explained later. The second is a simple read operation of the
Counter, which is selected with the A1, A0 inputs. The only
requirement is that the CLK input of the selected Counter
must be inhibited by using either the GATE input or external
logic. Otherwise, the count may be in process of changing
when it is read, giving an undefined result.
COUNTER LATCH COMMAND
The other method for reading the Counters involves a
special software command called the “Counter Latch
Command”. Like a Control Word, this command is written to
the Control Word Register, which is selected when A1, A0 =
11. Also, like a Control Word, the SC0, SC1 bits select one of
the three Counters, but two other bits, D5 and D4,
distinguish this command from a Control Word.
.
The selected Counter’s output latch (OL) latches the count
when the Counter Latch Command is received. This count is
held in the latch until it is read by the CPU (or until the Counter
is reprogrammed). The count is then unlatched automatically
and the OL returns to “following” the counting element (CE).
This allows reading the contents of the Counters “on the fly”
without affecting counting in progress. Multiple Counter Latch
Commands may be used to latch more than one Counter.
Each latched Counter’s OL holds its count until read. Counter
Latch Commands do not affect the programmed Mode of the
Counter in any way.
If a Counter is latched and then, some time later, latched
again before the count is read, the second Counter Latch
Command is ignored. The count read will be the count at the
time the first Counter Latch Command was issued.
With either method, the count must be read according to the
programmed format; specifically, if the Counter is
programmed for two byte counts, two bytes must be read.
The two bytes do not have to be read one right after the
other; read or write or programming operations of other
Counters may be inserted between them.
Another feature of the 82C54 is that reads and writes of the
same Counter may be interleaved; for example, if the
Counter is programmed for two byte counts, the following
sequence is valid.
1. Read least significant byte.
2. Write new least significant byte.
3. Read most significant byte.
4. Write new most significant byte.
If a counter is programmed to read or write two-byte counts,
the following precaution applies: A program MUST NOT
transfer control between reading the first and second byte to
another routine which also reads from that same Counter.
Otherwise, an incorrect count will be read.
READ-BACK COMMAND
The read-back command allows the user to check the count
value, programmed Mode, and current state of the OUT pin
and Null Count flag of the selected counter(s).
The command is written into the Control Word Register and
has the format shown in Figure 5. The command applies to
POSSIBLE PROGRAMMING SEQUENCE
A1 A0
Control Word - Counter 1 1 1
Control Word - Counter 0 1 1
LSB of Count - Counter 1 0 1
Control Word - Counter 2 1 1
LSB of Count - Counter 0 0 0
MSB of Count - Counter 1 0 1
LSB of Count - Counter 2 1 0
MSB of Count - Counter 0 0 0
MSB of Count - Counter 2 1 0
NOTE: In all four examples, all counters are programmed to
Read/Write two-byte counts. These are only four of many
programming sequences.
A1, A0 = 11; CS = 0; RD = 1; WR = 0
D7 D6 D5 D4 D3 D2 D1 D0
SC1SC000XXXX
SC1, SC0 - specify counter to be latched
SC1 SC0 COUNTER
00 0
01 1
10 2
1 1 Read-Back Command
D5, D4 - 00 designates Counter Latch Command, X - Don’t Care.
NOTE: Don’t Care bits (X) should be 0 to insure compatibility
with future products.

CS82C54-10Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Timers & Support Products PERIPH PRG-CNTR 5V 10MHZ 28PLCC COM
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New from this manufacturer.
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