MPC9351
MOTOROLA TIMING SOLUTIONS6
APPLICATIONS INFORMATION
Programming the MPC9351
The MPC9351 clock driver outputs can be configured into
several divider modes, in addition the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The output divider of the four
output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
“Output Frequency Relationship for an Example
Configuration” illustrates the various output configurations,
the table describes the outputs using the input clock
frequency CLK as a reference.
The output division settings establish the output
relationship, in addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to 200
MHz while the VCO frequency range is specified from 200
MHz to 400 MHz and should not be exceeded for stable
operation.
Output Frequency Relationship
a
for an Example Configuration
Inputs Outputs
FSELA FSELB FSELC FSELD QA QB QC QD
0 0 0 0 2 * CLK CLK CLK CLK
0 0 0 1 2 * CLK CLK CLK CLK ÷ 2
0 0 1 0 4 * CLK 2 * CLK CLK 2* CLK
0 0 1 1 4 * CLK 2 * CLK CLK CLK
0 1 0 0 2 * CLK CLK ÷ 2 CLK CLK
0 1 0 1 2 * CLK CLK ÷ 2 CLK CLK ÷ 2
0 1 1 0 4 * CLK CLK CLK 2 * CLK
0 1 1 1 4 * CLK CLK CLK CLK
1 0 0 0 CLK CLK CLK CLK
1 0 0 1 CLK CLK CLK CLK ÷ 2
1 0 1 0 2 * CLK 2 * CLK CLK 2 * CLK
1 0 1 1 2 * CLK 2 * CLK CLK CLK
1 1 0 0 CLK CLK ÷ 2 CLK CLK
1 1 0 1 CLK CLK ÷ 2 CLK CLK ÷ 2
1 1 1 0 2 * CLK CLK CLK 2 * CLK
1 1 1 1 2 * CLK CLK CLK CLK
a. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are
available by the connection of QA to the feedback input (EXT_FB).
Using the MPC9351 in zero–delay applications
Nested clock trees are typical applications for the
MPC9351. For these applications the MPC9351 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Motorola MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC9351 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC9351 PLL allows
for its use as a zero delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the
MPC9351 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t
(
∅
)
), I/O jitter
(t
JIT(∅)
, phase or long-term jitter), feedback path delay and
the output-to-output skew (t
SK(O)
relative to the feedback
output.
MPC9351 zero–delay configuration (feedback of QD4)
MPC9351
TCLK
QA
fref = 100 MHz
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
2 x 100 MHz
2 x 100 MHz
4 x 100 MHz
100 MHz (Feedback)
1
1
1
0
0
0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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