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MPC9351FA

P1-P3P4-P6P7-P9P10-P12
MPC9351
TIMING SOLUTIONS 7 MOTOROLA
Calculation of part-to-part skew
The MPC9351 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC9351 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
t
SK(PP)
= t
(
∅
)
+ t
SK(O)
+ t
PD,
LINE(FB)
+ t
JIT(
∅
)
CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 3. MPC9351 max. device-to-device skew
t
PD,LINE(FB)
t
JIT(∅)
+t
SK(O)
–t
(∅)
+t
(∅)
t
JIT(∅)
+t
SK(O)
t
SK(PP)
Max. skew
TCLK
Common
QFB
Device
1
Any Q
Device
1
QFB
Device2
Any Q
Device
2
Due to the statistical nature of I/O jitter a RMS value (1 ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8: Confidence Facter CF
CF Probability of clock edge within the distribution
± 1 0.68268948
± 2 0.95449988
± 3 0.99730007
± 4 0.99993663
± 5 0.99999943
± 6 0.99999999
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation a
I/O jitter confidence factor of 99.7% (± 3 ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of -251 ps to 351 ps relative to TCLK (V
CC
=3.3V and
f
VCO
= 400 MHz):
t
SK(PP)
= [–50ps...150ps] + [–150ps...150ps] +
[(17ps
–3)...(17ps 3)] + t
PD,
LINE(FB)
t
SK(PP)
= [–251ps...351ps] + t
PD,
LINE(FB)
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for V
CC
=3.3V (17 ps
RMS). I/O jitter is frequency dependant with a maximum at
the lowest VCO frequency (200 MHz for the MPC9351).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 4. and Figure 5. can be used to
derive a smaller I/O jitter number at the specific VCO
frequency, resulting in tighter timing limits in zero-delay mode
and for part-to-part skew t
SK(PP)
.
Figure 4. Max. I/O Jitter (RMS) versus frequency for
V
CC
=2.5V
Figure 5. Max. I/O Jitter (RMS) versus frequency for
V
CC
=3.3V
Power Supply Filtering
The MPC9351 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the
V
CCA
(PLL) power supply impacts the device characteristics,
for instance I/O jitter. The MPC9351 provides separate power
supplies for the output buffers (V
CC
) and the phase-locked
loop (V
CCA
) of the device.The purpose of this design
technique is to isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a digital system environment where it is more difficult
to minimize noise on the power supplies a second level of
isolation may be required. The simple but effective form of
isolation is a power supply filter on the V
CCA
pin for the
MPC9351. Figure 6. illustrates a typical power supply filter
scheme. The MPC9351 frequency and phase stability is
most susceptible to noise with spectral content in the 100kHz
to 20MHz range. Therefore the filter should be designed to
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MPC9351
MOTOROLA TIMING SOLUTIONS8
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop across the series
filter resistor R
F
. From the data sheet the I
CCA
current (the
current sourced through the V
CCA
pin) is typically 3 mA (5 mA
maximum), assuming that a minimum of 2.325V (V
CC
=3.3V
or V
CC
=2.5V) must be maintained on the V
CCA
pin. The
resistor R
F
shown in Figure 6. “V
CCA
Power Supply Filter”
must have a resistance of 270 (V
CC
=3.3V) or 9-10
(V
CC
=2.5V) to meet the voltage drop criteria.
Figure 6. V
CCA
Power Supply Filter
VCCA
VCC
MPC9351
10 nF
R
F
= 270Ω for V
CC
= 3.3V
R
F
= 9–10Ω for V
CC
= 2.5V
C
F
33...100 nF
R
F
VCC
C
F
= 1 µF for V
CC
= 3.3V
C
F
= 22 µF for V
CC
= 2.5V
The minimum values for R
F
and the and the filter capacitor
C
F
are defined by the required filter characteristics: the RC
filter should provide an attenuation greater than 40 dB for
noise whose spectral content is above 100 kHz. In the
example RC filter shown in Figure 6. “V
CCA
Power Supply
Filter”, the filter cut-off frequency is around 3-5 kHz and the
noise attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9351 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Driving Transmission Lines
The MPC9351 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to V
CC
÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9351 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 7. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9351 clock driver is effectively doubled due to its
capability to drive multiple lines.
Figure 7. Single versus Dual Transmission Lines
14Ω
IN
MPC9351
OUTPUT
BUFFER
R
S
= 36Ω
Z
O
= 50Ω
OutA
14Ω
IN
MPC9351
OUTPUT
BUFFER
R
S
= 36Ω
Z
O
= 50Ω
OutB0
R
S
= 36Ω
Z
O
= 50Ω
OutB1
The waveform plots in Figure 8. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9351 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9351. The output waveform in Figure 8. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
V
L
= V
S
( Z
0
÷ (R
S
+R
0
+Z
0
))
Z
0
= 50Ω || 50Ω
R
S
= 36Ω || 36Ω
R
0
= 14Ω
V
L
= 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
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MPC9351
TIMING SOLUTIONS 9 MOTOROLA
Figure 8. Single versus Dual Waveforms
TIME (nS)
VOLTAGE (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 9. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
Figure 9. Optimized Dual Line Termination
14Ω
MPC9351
OUTPUT
BUFFER
R
S
= 22Ω
Z
O
= 50Ω
R
S
= 22Ω
Z
O
= 50Ω
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 10. TCLK MPC9351 AC test reference for V
cc
= 3.3V and V
cc
= 2.5V
Figure 11. PCLK MPC9351 AC test reference
Pulse
Generator
Z = 50
R
T
= 50Ω
Z
O
= 50Ω
R
T
= 50Ω
Z
O
= 50Ω
MPC9351 DUT
V
TT
V
TT
Differential
Pulse Generator
Z = 50
R
T
= 50Ω
Z
O
= 50Ω
R
T
= 50Ω
Z
O
= 50Ω
MPC9351 DUT
V
TT
V
TT
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cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
P1-P3P4-P6P7-P9P10-P12

MPC9351FA

Mfr. #:
Buy MPC9351FA
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL1-9 LVCMOS/LVPECL LVCMOS PLL Clk Gen
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