ADP1821ARQZ-R7 Datasheet ADP1821ARQZ-R7 | P10-P12

ADP1821

Rev. C | Page 9 of 24

THEORY OF OPERATION

The ADP1821 is a versatile, economical, synchronous-rectified,

fixed-frequency, PWM, voltage mode step-down controller

capable of generating an output voltage as low as 0.6 V. It is ideal

for a wide range of high power applications, such as DSP power

and processor core power in telecommunications, medical

imaging, and industrial applications. The ADP1821 controller

operates from a 3.7 V to 5.5 V supply with a power input voltage

ranging from 1.0 V to 24 V.

The ADP1821 operates at a fixed, internally set 300 kHz or

600 kHz switching frequency that is controlled by the state of

the FREQ input. The high frequency reduces external compo-

nent size and cost while maintaining high efficiency. For noise

sensitive applications where the switching frequency needs to be

more tightly controlled, synchronize the ADP1821 to an external

signal whose frequency is between 300 kHz and 1.2 MHz.

The ADP1821 includes adjustable soft start with output reverse-

current protection, and a unique adjustable, lossless current

limit. It operates over the −40°C to +125°C temperature range

and is available in a space-saving, 16-lead QSOP.

SOFT START

When powering up or resuming operation after shutdown, over-

load, or short-circuit conditions, the ADP1821 employs an

adjustable soft start feature that reduces input current transients

and prevents output voltage overshoot at start-up and overload

conditions. The soft start period is set by the value of the soft

start capacitor, C

, between SS and GND.

When starting the ADP1821, C

is initially discharged. It is

enabled when

SHDN

is high and VCC is above the undervoltage

lockout threshold. C

begins charging to 0.8 V through an

internal 100 k resistor. As C

charges, the regulation voltage at

FB is limited to the lesser of either the voltage at SS or the internal

0.6 V reference voltage. As the voltage at SS rises, the output

voltage rises proportionally until the voltage at SS exceeds 0.6 V. At

this time, the output voltage is regulated to the desired voltage.

If the output voltage is precharged prior to turn-on, the ADP1821

limits reverse inductor current, which would discharge the output

voltage. Once the voltage at SS exceeds the 0.6 V regulation voltage,

the reverse current is re-enabled to allow the output voltage

regulation to be independent of load current.

ERROR AMPLIFIER

The ADP1821 error amplifier is an operational amplifier. The

ADP1821 senses the output voltages through an external

resistor divider at the FB pin. The FB pin is the inverting input

to the error amplifier. The error amplifier compares this feed-

back voltage to the internal 0.6 V reference, and the output of

the error amplifier appears at the COMP pin. The COMP pin

voltage then directly controls the duty cycle of the switching

converter.

A series/parallel RC network is tied between the FB pin and the

COMP pin to provide the compensation for the buck converter

control loop. A detailed design procedure for compensating the

system is provided in the

Compensating the Voltage Mode Buck

Regulator

section.

The error amplifier output is clamped between a lower limit of

about 0.7 V and a higher limit of about 2.4 V. When the COMP pin

is low, the switching duty cycle goes to 0%, and when the COMP

pin is high, the switching duty cycle goes to the maximum.

The SS pin is an auxiliary positive input to the error amplifier.

Whichever voltage is lowest, SS or the internal 0.6 V reference,

controls the FB pin voltage and thus the output. As a conse-

quence, if two of these inputs are close to each other, a small

offset is imposed on the error amplifier.

CURRENT-LIMIT SCHEME

The ADP1821 employs a unique, programmable, cycle-by-cycle,

lossless current-limit circuit that uses an ordinary, inexpensive

resistor to set the threshold. Every switching cycle, the synchronous

rectifier turns on for a minimum time and the voltage drop across

the MOSFET R

DSON

is measured to determine if the current is

too high.

This measurement is done by an internal current limit com-

parator and an external current-limit set resistor. The resistor

is connected between the switch node (that is the drain of the

rectifier MOSFET) and the CSL pin. The CSL pin, which is the

inverting input of the comparator, forces 50 A through the

resistor to create an offset voltage drop across it.

When the inductor current is flowing in the MOSFET rectifier,

its drain is forced below PGND by the voltage drop across its

DSON

. If the R

DSON

voltage drop exceeds the preset drop on the

current-limit set resistor, the inverting comparator input is

similarly forced below PGND and an overcurrent fault is flagged.

The normal transient ringing on the switch node is ignored

for 100 ns after the synchronous rectifier turns on, therefore,

the over current condition must also persist for 100 ns for a

fault to be flagged.

When the ADP1821 senses an overcurrent condition, the next

switching cycle is suppressed, the soft start capacitor is discharged

through an internal 2.5 k resistor, and the error amplifier

output voltage is pulled down. The output behaves like a

constant current source around the preset current limit when

the overcurrent condition exists. The ADP1821 remains in this

mode for as long as the overcurrent condition persists. In the

event of a short circuit, the short-circuit output current is the

current limit set by the R

resistor and is monitored cycle by

cycle. When the overcurrent condition is removed, operation

resumes in soft start mode.

The ADP1821 also offers a technique for implementing a

current-limit foldback in the event of a short circuit with the

use of an additional resistor. See the

Setting the Current Limit

section for more information.

ADP1821

Rev. C | Page 10 of 24

MOSFET DRIVERS

The DH pin drives the high-side switch MOSFET. This is a

boosted 5 V gate driver that is powered by a bootstrap capacitor

circuit. This configuration allows the high-side, N-channel

MOSFET gate to be driven above the input voltage, allowing full

enhancement and a low voltage drop across the MOSFET. The

bootstrap capacitor is connected from the SW pin to the BST

pin. A bootstrap Schottky diode connected from the PVCC pin

to the BST pin recharges the bootstrap capacitor every time the

SW node goes low. Use a bootstrap capacitor value greater than

100× the high-side MOSFET input capacitance.

In practice, the switch node can run up to 24 V of input voltage,

and the boost nodes can operate more than 5 V above this to

allow full gate drive. The power input voltage can be run from

1 V to 24 V.

The switching cycle is initiated by the internal clock signal. The

high-side MOSFET is turned on by the DH driver, and the SW

node goes high, pulling up on the inductor. When the internally

generated ramp signal crosses the COMP pin voltage, the switch

MOSFET is turned off and the low-side synchronous rectifier

MOSFET is turned on by the DL driver. Active break-before-

make circuitry as well as a supplemental fixed dead time are

used to prevent cross-conduction in the switches.

The DL pin provides the gate drive for the low-side MOSFET

synchronous rectifier. Internal circuitry monitors the external

MOSFETs to ensure break-before-make switching to prevent

cross-conduction. An active dead-time reduction circuit

reduces the break-before-make time of the switching to limit

the losses due to current flowing through the synchronous

rectifier body diode.

The PVCC pin provides power to the low-side drivers. It is

limited to 5.5 V maximum input and should have a local

decoupling capacitor to PGND.

The synchronous rectifier is turned on for a minimum time

of about 200 ns on every switching cycle in order to sense the

current. This and the nonoverlap dead time put a limit on the

maximum high-side switch duty cycle based on the selected

switching frequency. Typically, this is about 90% at 300 kHz

switching, and at 1 MHz switching, it reduces to about 70%

maximum duty cycle.

INPUT VOLTAGE RANGE

The ADP1821 takes its internal power from the VCC and PVCC

inputs. PVCC powers the low-side MOSFET gate drive (DL),

and VCC powers the internal control circuitry. Both of these

inputs are limited to between 3.7 V and 5.5 V. Bypass PVCC to

PGND with a 1 µF or greater capacitor. Bypass VCC to GND

with a 0.1 µF or greater capacitor.

The power input to the dc-to-dc converter can range between

1.2× the output voltage and 24 V. Bypass the power input to

PGND with a suitably large capacitor. See the

Selecting the

Input Capacitor

section.

SETTING THE OUTPUT VOLTAGE

The output voltage is set using a resistive voltage divider from

the output to FB. The voltage divider drops the output voltage

to the 0.6 V FB regulation voltage to set the regulation output

voltage. The output voltage is set to voltages as low as 0.6 V and

as high as 85% of the minimum power input voltage (see the

Feedback Voltage Divider section).

SWITCHING FREQUENCY CONTROL AND

SYNCHRONIZATION

The ADP1821 has a logic-controlled frequency select input (FREQ)

which sets the switching frequency to 300 kHz or 600 kHz. Drive

FREQ low for 300 kHz and high for 600 kHz.

The SYNC input is used to synchronize the converter switching

frequency to an external signal. The converter switching can be

synchronized to an external signal. This allows multiple ADP1821

converters to be operated at the same frequency to prevent

frequency beating or other interactions.

To synchronize the ADP1821 switching to an external signal,

drive the SYNC input with a synchronizing signal. The ADP1821

can only synchronize up to 2× the nominal oscillator frequency.

If the frequency is set to 300 kHz (FREQ connected to GND),

then the synchronization frequency needs to be in between

300 kHz and 600 kHz. Since the 300 kHz setting has a mini-

mum specification (see

Table 1) of 250 kHz and a maximum

of 375 kHz over the specified temperature range, the recom-

mended synchronization frequency range is between 375 kHz

and 500 kHz to cover the whole range of part-to-part variation

and over the operating temperature range. If the frequency is set

to 600 kHz (FREQ connected to VCC), then the synchronization

frequency needs to be in between 600 kHz and 1.2 MHz. Since

the 600 kHz setting has a minimum specification (see

Table 1)

of 470 kHz and a maximum of 720 kHz over the specified tem-

perature range, the recommended synchronization frequency

range is between 720 kHz and 940 kHz to cover the whole range

of part-to-part variation and over the operating temperature

range. Driving SYNC faster than recommended for the FREQ

setting results in a small ramp signal, which could affect the

signal-to-noise ratio and the modulator gain and stability.

When an external clock is detected at the first SYNC edge,

the internal oscillator is reset and clock control shifts to SYNC.

The SYNC edges then trigger subsequent clocking of the PWM

outputs. The DH rising edges appear about 320 ns after the cor-

responding SYNC edge, and the frequency is locked to the

external signal. If the external SYNC signal disappears during

operation, the ADP1821 reverts to its internal oscillator and

experiences a delay of no more than a single cycle of the

internal oscillator.

ADP1821

Rev. C | Page 11 of 24

COMPENSATION

The control loop is compensated by an external series RC

network from COMP to FB and sometimes requires a series

RC in parallel with the top voltage divider resistor. COMP is

the output of the internal error amplifier.

The internal error amplifier compares the voltage at FB to the

internal 0.6 V reference voltage. The difference between the two

(the feedback voltage error) is amplified by the error amplifier.

To optimize the ADP1821 for stability and transient response

for a given set of external components and input/output voltage

conditions, choose the compensation components carefully. For

more information on choosing the compensation components,

see the

Compensating the Voltage Mode Buck Regulator section.

POWER-GOOD INDICATOR

The ADP1821 features an open-drain, power-good output

(PWGD) that sinks current when the output voltage drops 8.3%

below or 25% above the nominal regulation voltage. Two com-

parators measure the voltage at FB to set these thresholds. The

PWGD comparator directly monitors FB, and the threshold is

fixed at 0.55 V for undervoltage and 0.75 V for overvoltage. The

PWGD output also sinks current if an overtemperature or input

undervoltage condition is detected and is operational with VCC

voltage as low as 1 V.

Use this output as a logical power-good signal by connecting a

pull-up resistor from PWGD to an appropriate supply voltage.

THERMAL SHUTDOWN

The ADP1821 controller does not generate much heat under

normal conditions, even when driving a relatively large MOSFET.

However, the surrounding power components or other circuits

on the same PCB could heat up the PCB to an unsafe operating

temperature. The ADP1821 controller goes into shutdown and

shuts off the gate drivers when its junction temperature reaches

about 145°C. When the junction temperature drops below

about 135°C, the ADP1821 resumes normal operation in a soft

start mode.

SHUTDOWN CONTROL

The ADP1821 dc-to-dc converter features a low power shut-

down mode that reduces quiescent supply current to 1 A. To

shut down the ADP1821, drive

SHDN

low. To turn it on, drive

SHDN

high. For automatic startup, connect

SHDN

to VCC.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADP1821ARQZ-R7

Mfr. #:

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Manufacturer:

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Description:

Switching Controllers 20 Amp Buck Controller in QSOP

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