ADP1821
Rev. C | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DH
SW
SYNC
PWGD
SHDN
FREQ
BST
DL
PGND
CSL
FB
GND SS
COMP
VCC
PVCC
TOP VIEW
(Not to Scale)
ADP1821
05310-004
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 BST
High-Side Gate Driver Boost Capacitor Input. A capacitor between SW and BST powers the high-side gate driver, DH.
The capacitor is charged through a diode from PVCC when the low-side MOSFET is on. Connect a 0.1 µF or greater
ceramic capacitor from BST to SW and a Schottky diode from PVCC to BST to power the high-side gate driver.
2 DH
High-Side Gate Driver Output. Connect DH to the gate of the external high-side, N-channel MOSFET switch. DH is
powered from the capacitor between SW and BST, and its voltage swings between V
SW
and V
BST
.
3 SW
Power Switch Node. Connect the source of the high-side, N-channel MOSFET switch and the drain of the low-side,
N-channel MOSFET synchronous rectifier to SW. SW powers the output through the output LC filter.
4 SYNC
Frequency Synchronization Input. Drive SYNC with an external 300 kHz to 1.2 MHz signal to synchronize the converter
switching frequency to the applied signal. The maximum SYNC frequency is limited to 2 times the nominal internal
frequency selected by FREQ. Do not leave SYNC unconnected; when not used, connect SYNC to GND.
5 FREQ
Frequency Select Input. FREQ selects the converter switching frequency. Drive FREQ low to select 300 kHz, or high
to select 600 kHz. Do not leave FREQ unconnected.
6
SHDN Active Low, DC-to-DC Shutdown Input. Drive SHDN high to turn on the converter and low to turn it off. Connect
SHDN to VCC for automatic startup.
7 PWGD
Open-Drain, Power-Good Output. PWGD sinks current to GND when the output voltage is above or below the
regulation voltage. Connect a pull-up resistor from PWGD to VDD for a logical power-good indicator.
8 GND Analog Ground. Connect GND to PGND at a single point as close as possible to the internal circuitry (IC).
9 SS
Soft Start Control Input. A capacitor from SS to GND controls the soft start period. When the output is overloaded,
SS is discharged to prevent excessive input current while the output recovers. Connect a 1 nF capacitor to a 1 µF
capacitor from SS to GND to set the soft start period. See the
Soft Start section.
10 FB
Voltage Feedback Input. Connect to a resistive voltage divider from the output to FB to set the output voltage. See
the
Setting the Output Voltage section.
11 COMP
Compensation Node. Connect a resistor-capacitor network from COMP to FB to compensate the regulation control
system. See the
Compensation section.
12 VCC
Internal Power Supply Input. VCC powers the internal circuitry. Bypass VCC to GND with a 0.1 µF or greater
capacitor connected as close as possible to the IC.
13 CSL
Low-Side Current Sense Input. Connect CSL to SW through a resistor to set the current limit. See the
Setting the
Current Limit
section.
14 PGND Power Ground. Connect GND to PGND at a single point as close as possible to the IC.
15 DL
Low-Side Gate Driver Output. Connect DL to the gate of the low-side, N-channel MOSFET synchronous rectifier. The
DL voltage swings between PGND and PVCC.
16 PVCC
Internal Gate Driver Power Supply Input. PVCC powers the low-side gate driver, DL. Bypass PVCC to PGND with a
1 µF or greater capacitor connected as close as possible to the IC.
