ADP1821ARQZ-R7 Datasheet ADP1821ARQZ-R7 | P13-P15

ADP1821

Rev. C | Page 12 of 24

APPLICATION INFORMATION

SELECTING THE INPUT CAPACITOR

The input current to a buck converter is a pulsed waveform. It is

zero when the high-side switch is off and approximately equal

to the load current when it is on. The input capacitor carries the

input ripple current, allowing the input power source to supply

only the dc current. The input capacitor needs sufficient ripple

current rating to handle the input ripple and the equivalent series

resistance (ESR) that is low enough to mitigate input voltage

ripple. For the usual current ranges for these converters, good

practice is to use two parallel capacitors placed close to the drains

of the high-side switch MOSFETs, one bulk capacitor of suffi-

ciently high current rating as calculated in Equation 1, along

with 10 F of ceramic capacitor.

Select an input bulk capacitor based on its ripple current rating.

First, determine the duty cycle of the output with the larger load

current by

OUT

D =

(1)

Second, determine the input capacitor ripple current, which is

approximately

()

LRIPPLE

−

≈

(2)

where:

is the maximum inductor or load current for the channel.

D is the duty cycle.

Use this method to determine the input capacitor ripple current

rating for duty cycles between 20% and 80%.

For duty cycles less than 20% or greater than 80%, use an input

capacitor with a ripple current rating of

RIPPLE

> 0.4 I

(3)

OUTPUT LC FILTER

The output LC filter smoothes the switched voltage at SW,

making the output voltage an almost dc voltage. Choose the

output LC filter to achieve the desired output ripple voltage.

Because the output LC filter is part of the regulator negative-

feedback control loop, the choice of the output LC filter

components affects the regulation control loop stability.

Choose an inductor value such that the inductor ripple current

is approximately 1/3 of the maximum dc output load current.

Using a larger value inductor results in a physical size larger

than required and using a smaller value results in increased

losses in the inductor and/or MOSFET switches.

Use the following equation to choose the inductor value:

⎥

⎦

⎤

⎢

⎣

⎡

−

Δ×

OUT

L 1

(4)

where:

L is the inductor value.

is the switching frequency.

OUT

is the output voltage.

is the input voltage.

ΔI

is the inductor ripple current, typically 1/3 of the maximum

dc load current.

Choose the output bulk capacitor to set the desired output voltage

ripple. The impedance of the output capacitor at the switching

frequency multiplied by the ripple current gives the output

voltage ripple. The impedance is made up of the capacitive

impedance plus the nonideal parasitic characteristics, the ESR

and the equivalent series inductance (ESL). The output voltage

ripple can be approximated with

)4(

ESLf

ESRIV

OUT

⎟

⎠

⎞

⎜

⎝

⎛

+Δ=Δ

(5)

where:

ΔV

OUT

is the output ripple voltage.

ΔI

is the inductor ripple current.

ESR is the equivalent series resistance of the output capacitor

(or the parallel combination of ESR of all output capacitors).

ESL is the equivalent series inductance of the output capacitor

(or the parallel combination of ESL of all capacitors).

Note that the factors of 8 and 4 in Equation 5 would normally

be 2π for sinusoidal waveforms, but the ripple current wave-

form in this application is triangular. Parallel combinations

of different types of capacitors, for example, a large aluminum

electrolytic in parallel with MLCCs, may give different results.

Usually the impedance is dominated by ESR at the switching

frequency so this equation reduces to

ESRIV

OUT

≅

(6)

Electrolytic capacitors have significant ESL also, on the order

of 5 nH to 20 nH, depending on type, size, and geometry; and

PCB traces contribute some ESR and ESL as well. However,

using the maximum ESR rating from a capacitor data sheet

usually provides some margin such that measuring the ESL is

not usually required.

ADP1821

Rev. C | Page 13 of 24

In the case of output capacitors where the impedance of the

ESR and ESL are small at the switching frequency, for instance,

where the output capacitor is a bank of parallel MLCC capaci-

tors, the capacitive impedance dominates and the ripple

equation reduces to

OUT

≅Δ

(7)

Make sure that the ripple current rating of the output capacitors

is greater than the maximum inductor ripple current.

During a load step transient on the output, the output capacitor

supplies the load until the control loop has a chance to ramp the

inductor current. This initial output voltage deviation due to a

change in load is dependent on the output capacitor character-

istics. Again, usually the capacitor ESR dominates this response,

and the V

OUT

in Equation 6 can be used with the load step

current value for I

SELECTING THE MOSFETS

The choice of MOSFET directly affects the dc-to-dc converter

performance. The MOSFET must have low on resistance to reduce

R losses and low gate charge to reduce transition losses. In

addition, the MOSFET must have low thermal resistance to

ensure that the power dissipated in the MOSFET does not result

in excessive MOSFET die temperature.

The high-side MOSFET carries the load current during on time

and carries all the transition losses of the converter. Typically,

the lower the MOSFET on resistance, the higher the gate charge

and vice versa. Therefore, it is important to choose a high-side

MOSFET that balances the two losses. The conduction loss of

the high-side MOSFET is determined by the equation

()

⎟

⎠

⎞

⎜

⎝

⎛

≅

OUT

DSONLOADC

RIP

(8)

where:

is the conduction power loss.

DSON

is the MOSFET on resistance.

The gate charging loss is approximated by the equation

SWGPVCCG

fQVP ≅

(9)

where:

is the gate charging loss power.

PVCC

is the gate driver supply voltage.

is the MOSFET total gate charge.

is the converter switching frequency.

The high-side MOSFET transition loss is approximated by the

equation

(

)

LOAD

fttIV

(10)

where:

is the high-side MOSFET switching loss power.

is the MOSFET rise time.

is the MOSFET fall time.

The total power dissipation of the high-side MOSFET is the

sum of all the previous losses, or

≅

(11)

where P

is the total high-side MOSFET power loss.

The conduction losses may need an adjustment to account

for the MOSFET R

DSON

variation with temperature. Note that

MOSFET R

DSON

increases with increasing temperature. A MOSFET

data sheet should list the thermal resistance of the package, θ

along with a normalized curve of the temperature coefficient of

the R

DSON

. For the power dissipation estimated above, calculate

the MOSFET junction temperature rise over the ambient

temperature of interest.

= T

+ θ

(12)

Then calculate the new R

DSON

from the temperature coefficient

curve and the R

DSON

spec at 25°C. A typical value of the temperature

coefficient (TC) of the R

DSON

is 0.004/°C, thus, an alternate

method to calculate the MOSFET R

DSON

at a second

temperature, T

, is

DSON

@ T

= R

DSON

@ 25°C(1 + TC(T

− 25°C)) (13)

Next, the conduction losses can be recalculated and the pro-

cedure iterated once or twice until the junction temperature

calculations are relatively consistent.

The synchronous rectifier, or low-side MOSFET, carries the

inductor current when the high-side MOSFET is off. The low-

side MOSFET transition loss is small and can be neglected in

the calculation. For high input voltage and low output voltage,

the low-side MOSFET carries the current most of the time.

Therefore, to achieve high efficiency, it is critical to optimize

the low-side MOSFET for low on resistance. In cases where the

power loss exceeds the MOSFET rating or lower resistance is

required than is available in a single MOSFET, connect multiple

low-side MOSFETs in parallel. The equation for low-side

MOSFET power loss is

()

⎥

⎦

⎤

⎢

⎣

⎡

−≅

OUT

DSONLOADLS

RIP 1

(14)

where:

is the low-side MOSFET on resistance.

DSON

is the total on resistance of the low-side MOSFET(s).

Check the gate charge losses of the synchronous rectifier

using the P

equation (Equation 9) to be sure it is reasonable.

If multiple low-side MOSFETs are used in parallel, then use

the parallel combination of the on resistances for determining

DSON

to solve this equation.

ADP1821

Rev. C | Page 14 of 24

SETTING THE CURRENT LIMIT

The current-limit comparator measures the voltage across the

low-side MOSFET to determine the load current.

The current limit is set through the current-limit resistor, R

CSL, the current sense pin, sources 50 A through R

. This

creates an offset voltage of R

multiplied by the 50 A CSL

current. When the drop across the low-side MOSFET R

DSON

equal to or greater than this offset voltage, the ADP1821 flags

a current-limit event.

Because the CSL current and the MOSFET R

DSON

vary over process

and temperature, the minimum current limit should be set to

ensure that the system can handle the maximum desired load

current. To do this, use the peak current in the inductor, which

is the desired current-limit level plus the ripple current, the

maximum R

DSON

of the MOSFET at its highest expected tem-

perature, and the minimum CSL current.

A42

)(MAX

DSON

LPK

R =

(15)

where I

LPK

is the peak inductor current.

When an overcurrent event occurs, the overcurrent comparator

prevents switching cycles until the rectifier current has decayed

below the threshold. The overcurrent comparator is blanked for

the first 100 ns of the synchronous rectifier cycle to prevent

switch node ringing from falsely tripping the current limit.

The

ADP1821 senses the current limit during the off cycle. When

the current-limit condition occurs, the output behaves like a

constant current source around the preset current limit. When

the overload condition is removed, the output recovers with the

normal soft start slope and does not overshoot.

In the event of a short circuit, the ADP1821 offers a technique

for implementing a current-limit foldback with the use of an

additional resistor, as shown in Figure 15. Resistor R

is largely

responsible for setting the foldback current limit during a short

circuit, and Resistor R

is mainly responsible for setting up the

normal current limit. R

is lower than R

. These current-limit

sense resistors can be calculated as

MAXDSONPKFOLDBACK

)(

(16)

MAXDSON

LPK

OUT

)(

−

(17)

where:

PKFOLDBACK

is the desired short circuit peak inductor current limit.

LPK

is the peak inductor current limit during normal operation

and is also used in Equation 15.

ADP1821

CSL

OUT

05310-023

Figure 15. Short-Circuit Current Foldback Scheme

Because the buck converter is usually running at a fairly high

current, PCB layout and component placement may affect

the current-limit setting. An iteration of the R

or R

and R

values may be required for a particular board layout and MOSFET

selection. If alternate MOSFETs are substituted at some point in

production, these resistor values may also need an iteration.

FEEDBACK VOLTAGE DIVIDER

The output regulation voltage is set through the feedback voltage

divider. The output voltage is reduced through the voltage

divider and drives the FB feedback input. The regulation

threshold at FB is 0.6 V. The maximum input bias current into

FB is 100 nA. For a 0.15% degradation in regulation voltage and

with 100 nA bias current, the low-side resistor, R

BOT

, needs to be

less than 9 kΩ, which results in 67 µA of divider current. For

BOT

, use 1 k to 10 k. A larger value resistor can be used, but

results in a reduction in output voltage accuracy due to the

input bias current at the FB pin, whereas lower values cause

increased quiescent current consumption. Choose R

TOP

to set

the output voltage by using the following equation:

⎟

⎠

⎞

⎜

⎝

⎛

OUT

BOTTOP

(18)

where:

TOP

is the high-side voltage divider resistance.

BOT

is the low-side voltage divider resistance.

OUT

is the regulated output voltage.

is the feedback regulation threshold, 0.6 V.

COMPENSATING THE VOLTAGE MODE BUCK

REGULATOR

Assuming the LC filter design is complete, the feedback control sys-

tem can be compensated. Good compensation is critical to proper

operation of the regulator. Calculate the quantities in Equation 19

through Equation 47 to derive the compensation values.

The goal is to guarantee that the voltage gain of the buck con-

verter crosses unity at a slope that provides adequate phase margin

for stable operation. Additionally, at frequencies above the cross-

over frequency, f

, guaranteeing sufficient gain margin and

attenuation of switching noise are important secondary goals.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

ADP1821ARQZ-R7

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