ADP1821
Rev. C | Page 15 of 24
For initial practical designs, a good choice for the crossover
frequency is 1/10 of the switching frequency; first calculate
10
SW
CO
f
f =
(19)
This gives sufficient frequency range to design a compensation
that attenuates switching artifacts, yet also gives sufficient
control loop bandwidth to provide good transient response.
The output LC filter is a resonant network that inflicts two poles
upon the response at a Frequency f
LC
, so next calculate
LCπ
f
LC
2
1
=
(20)
The LC corner frequency is about two orders of magnitude
below the switching frequency, and therefore about one order of
magnitude below crossover. To achieve sufficient phase margin
at crossover to guarantee stability, the design must compensate
for the two poles at the LC corner frequency with two zeros to
boost the system phase prior to crossover. The two zeros require
an additional pole or two above the crossover frequency to
guarantee adequate gain margin and attenuation of switching
noise at high frequencies.
Depending on component selection, one zero might already be
generated by the ESR of the output capacitor. Calculate this zero
corner frequency,
f
ESR
, as
OUT
ESR
ESR
CRπ
f
2
1
= (21)
This zero is often near or below crossover and is useful in
bringing back some of the phase lost at the LC corner.
Figure 16 shows a typical bode plot of the LC filter by itself.
The gain of the LC filter at crossover can be linearly
approximated from
Figure 16 as
ESRLC
FILTER
AAA +=
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×−
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×−=
ESR
CO
LC
ESR
FILTER
f
f
f
f
A logdB20logdB40
(22)
If f
ESR
≈ f
CO
, then add another 3 dB to account for the local
difference between the exact solution and the preceding linear
approximation.
To compensate the control loop, the gain of the system must be
brought back up so that it is 0 dB at the desired crossover
frequency. Some gain is provided by the PWM modulation
itself, and it is given by
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
RAMP
IN
MOD
V
V
A log20
(23)
For systems using the internal oscillator, this becomes
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
V25.1
log20
IN
MOD
V
A
(24)
0dB
GAIN
FREQUENCY
LC FILTER BODE PLOT
PHASE
f
LC
f
ESR
f
CO
f
SW
A
FILTER
–40dB/dec
Φ
FILTER
0°
–90°
–180°
–20dB/dec
05310-015
Figure 16. LC Filter Bode Plot
Note that if the converter is being synchronized, the ramp
voltage, V
RAMP
, is lower than 1.25 V by the percentage of
frequency increase over the nominal setting of the FREQ pin
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
SYNC
FREQ
RAMP
f
f
V V25.1
(25)
The rest of the system gain is needed to reach 0 dB at crossover.
The total gain of the system therefore, is given by
A
T
= A
MOD
+ A
FILTER
+ A
COMP
(26)
where:
A
MOD
is the gain of the PWM modulator.
A
FILTER
is the gain of the LC filter including the effects of the
ESR zero.
A
COMP
is the gain of the compensated error amplifier.
Additionally, the phase of the system must be brought back up
to guarantee stability. Note from the bode plot of the filter that
the LC contributes −180° of phase shift. Additionally, because
the error amplifier is an integrator at low frequency, it contrib-
utes an initial −90°. Therefore, before adding compensation or
accounting for the ESR zero, the system is already down −270°.
To avoid loop inversion at crossover, or −180° phase shift, a
good initial practical design is to require a phase margin of 60°,
which gives an overall phase loss of −120° from the initial low
frequency dc phase. The goal of the compensation is to boost
the phase back up from −270° to −120° at crossover.
