IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
3
1414G—08/15/12
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 VDD PWR Power supply, nominal 3.3V
2 DIF_IN IN 0.7 V Differential TRUE input
3 DIF_IN# IN 0.7 V Differential Complementary Input
4 GND PWR Ground pin.
5OE0# IN
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
6 DIF_0 OUT 0.7V differential true clock output
7 DIF_0# OUT 0.7V differential Complementary clock output
8 VDD PWR Power supply, nominal 3.3V
9 GND PWR Ground pin.
10 OE1# IN
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
11 DIF_1 OUT 0.7V differential true clock output
12 DIF_1# OUT 0.7V differential Complementary clock output
13 OE2# IN
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
14 DIF_2 OUT 0.7V differential true clock output
15 DIF_2# OUT 0.7V differential Complementary clock output
16 GND PWR Ground pin.
17 VDD PWR Power supply, nominal 3.3V
18 OE3# IN
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
19 DIF_3 OUT 0.7V differential true clock output
20 DIF_3# OUT 0.7V differential Complementary clock output
21 OE4# IN
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
22 DIF_4 OUT 0.7V differential true clock output
23 DIF_4# OUT 0.7V differential Complementary clock output
24 VDD PWR Power supply, nominal 3.3V
25 GND PWR Ground pin.
26 OE5# IN
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
27 DIF_5 OUT 0.7V differential true clock output
28 DIF_5# OUT 0.7V differential Complementary clock output
29 **ADR_SEL IN
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
30 HIGH_BW# IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
31 FS2 IN Frequency select pin.
32 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
