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9DB1200CGLF

P1-P3P4-P6P7-P9P10-P12P13-P14
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
4
1414G—08/15/12
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
33 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
34 FS1 IN 3.3V Frequency select latched input pin.
35 BYPASS#/PLL IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
36 VTTPWRGD#/PD IN
VTTPWRGD# is an active low input used to sample latched inputs and
allow the device to Power Up. PD is an asynchronous active high input
pin used to put the device into a low power state. The internal clocks and
PLLs are stopped.
37 DIF_6# OUT 0.7V differential complement clock output
38 DIF_6 OUT 0.7V differential true clock output
39 OE6# IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
40 GND PWR Ground pin.
41 VDD PWR Power supply, nominal 3.3V
42 DIF_7# OUT 0.7V differential complement clock output
43 DIF_7 OUT 0.7V differential true clock output
44 OE7# IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
45 DIF_8# OUT 0.7V differential complement clock output
46 DIF_8 OUT 0.7V differential true clock output
47 OE8# IN
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
48 VDD PWR Power supply, nominal 3.3V
49 GND PWR Ground pin.
50 DIF_9# OUT 0.7V differential complement clock output
51 DIF_9 OUT 0.7V differential true clock output
52 OE9# IN
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
53 DIF_10# OUT 0.7V differential complement clock output
54 DIF_10 OUT 0.7V differential true clock output
55 OE10# IN
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
56 GND PWR Ground pin.
57 VDD PWR Power supply, nominal 3.3V
58 DIF_11# OUT 0.7V differential complement clock output
59 DIF_11 OUT 0.7V differential true clock output
60 OE11# IN
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
61 FS0 IN 3.3V Frequency select latched input pin.
62 IREF OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
63 AGND PWR Analog Ground pin for Core PLL
64 VDDA PWR 3.3V power for the PLL core.
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
5
1414G—08/15/12
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
Symbol Parameter Min Max Units
VDDA 3.3V Core Supply Voltage 4.6 V
VDD 3.3V Logic Supply Voltage 4.6 V
V
IL
Input Low Voltage GND-0.5 V
V
IH
Input High Voltage V
DD
+0.5V V
Ts Storage Temperature -65 150
°
C
Tambient Ambient Operating Temp 0 70 °C
Tcase Case Temperature 115 °C
ESD prot
Input ESD protection
human body model 2000 V
T
A
= 0 - 70°C; Supply Voltage V
D
D
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5% GND
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
D
D
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors -200 uA 1
Operating Supply Current I
DD3.3OP
Full Active, C
L
= Full load; 375 mA 1
Powerdown Current I
DD3.3P
D
all differential pairs tri-stated 24 mA 1
F
iPLL
PLL Mode 100 400 MHz 1
F
iBYPASS
Bypass Mode 33 400 MHz 1
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Peakin
g
when HIGH_BW#=0 1.5 2 dB 1
Peakin
g
when HIGH_BW#=1 1.5 2 dB 1
PLL Bandwidth when HIGH_BW#=0 2 3 4 MHz 1
PLL Bandwidth when HIGH_BW#=1 0.7 1 1.4 MHz 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input
clock stabilization or de-assertion of
PD# to 1st clock
1.8 ms 1,2
Modulation Frequency f
MOD
Triangular Modulation 30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4 12 cycles 1,3
Tdrive_PD t
DRVPD
DIF output enable after
PD de-assertion
300 us 1,3
Tfall t
F
Fall time of OE# 5 ns 1
Trise t
R
Rise time of OE# 5 ns 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timin
g
dia
g
rams for timin
g
requirements.
3
Time from deassertion until out
p
uts are >200 mV
Capacitance
Input Low Current
PLL Bandwidth BW
Input Frequency
PLL Jitter Peaking j
PEAK
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
6
1414G—08/15/12
Electrical Characteristics - Clock Input Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input High Voltage -
DIF_IN
V
IHDI F
Differential inputs
(single-ended measurement)
600 800 1150 mV 1
Input Low Voltage -
DIF_IN
V
ILDIF
Differential inputs
(single-ended measurement)
V
SS
- 300 0 300 mV 1
Input Common Mode
Voltage - DIF_IN
V
COM
Common Mode Input Voltage 300 1000 mV 1
Input Amplitude - DIF_IN V
SWING
Peak to Peak value 300 1450 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA 1
Input Duty Cycle d
tin
Measurement from differential
wavefrom
45 55 % 1
Input Jitter - Cycle to
Cycle
J
DI FI n
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through Vswing min centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω
, R
REF
=475
Ω
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Im
p
edance
Zo
1
V
O
= V
x
3000
Ω
1
Voltage High VHigh 660 850 1,3
Voltage Low VLow -150 150 1,3
Max Volta
g
eVovs 1150 1
Min Volta
eVuds -300 1
Crossin
g
Volta
g
e
(
abs
)
Vcross
(
abs
)
250 550 mV 1
Crossin
g
Volta
g
e
(
var
)
d-Vcross Variation of crossin
g
over all ed
g
es 140 mV 1
Lon
g
Accurac
y
pp
msee T
p
eriod min-max values 0
pp
m1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 700 ps 1
Rise Time Variation
d-t
r
125 ps 1
Fall Time Variation
d-t
f
125 ps 1
Duty Cycle
d
t3
Measurement from differential wavefrom 45 55 % 1
t
pdBYP
Bypass Mode, V
T
= 50%
2.5 4.5 ps 1
t
pdPLL
PLL Mode V
T
= 50%
-250 250 ps 1
Skew, Output to Output
t
sk3
V
T
= 50%
50 ps 1
PLL mode 50
p
s1,5
BYPASS mode as additive
j
itte
r
50
p
s1,5
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
4
A
pp
lies to B
yp
ass Mode Onl
y
5
Measured from differential waveform
Skew, Input to Output
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK410B+/CK509B accuracy requirements. The 9DB1200 itself does not contribute to ppm error.
Jitter, Cycle to cycle
t
jcyc-cyc
Statistical measurement on single ended
signal using oscilloscope math function.
mV
Measurement on single ended signal
using absolute value.
mV
P1-P3P4-P6P7-P9P10-P12P13-P14

9DB1200CGLF

Mfr. #:
Buy 9DB1200CGLF
Manufacturer:
IDT
Description:
Clock Buffer 12 OUTPUT PCIE GEN2 BUFFER w/QPI
Lifecycle:
New from this manufacturer.
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