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9DB1200CGLF

P1-P3P4-P6P7-P9P10-P12P13-P14
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
10
1414G—08/15/12
General SMBus serial interface information for the 9DB1200C
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC
(h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC
(h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD
(h)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Write Operation
Slave Address DC
(h)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address DD
(h)
Index Block Read Operation
Slave Address DC
(h)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
Note: Addresses show assumes pin 29 is low.
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
11
1414G—08/15/12
SMBus Table: Frequency Select Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
HIGH_BW# High or Low BW RW High BW Low BW Latch
Bit 6
BYPASS#/PLL B
y
pass (non-PLL Mode) or PLL Mode RW B
y
pass PLL Latch
Bit 5
Reserved Reserved RW X
Bit 4
Reserved Reserved RW X
Bit 3
Reserved Reserved RW X
Bit 2
FS2 Frequenc
y
Select 2 RW Latch
Bit 1
FS1 Frequency Select 1 RW Latch
Bit 0
FS0 Frequency Select 0 RW Latch
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
DIF_7 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 6
DIF_6 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 5
DIF_5 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 4
DIF_4 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 3
DIF_3 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 2
DIF_2 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 1
DIF_1 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 0
DIF_0 Output Control (Disable = Hi-Z) RW Disable Enable 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
Reserved Reserved RW 0
Bit 6
Reserved Reserved RW 0
Bit 5
Reserved Reserved RW 0
Bit 4
Reserved Reserved RW 0
Bit 3
DIF_11 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 2
DIF_10 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 1
DIF_9 Output Control (Disable = Hi-Z) RW Disable Enable 1
Bit 0
DIF_8 Output Control (Disable = Hi-Z) RW Disable Enable 1
SMBus Table: Output Enable Readback
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
OE7# OE# Pin Readback R Enabled Disabled X
Bit 6
OE6# OE# Pin Readback R Enabled Disabled X
Bit 5
OE5# OE# Pin Readback R Enabled Disabled X
Bit 4
OE4# OE# Pin Readback R Enabled Disabled X
Bit 3
OE3# OE# Pin Readback R Enabled Disabled X
Bit 2
OE2# OE# Pin Readback R Enabled Disabled X
Bit 1
OE1# OE# Pin Readback R Enabled Disabled X
Bit 0
OE0# OE# Pin Readback R Enabled Disabled X
-
- Reserved
B
y
te 0
-
-
Reserved
-
-
- Reserved
-
See FS Table
B
y
te 1
43,42
38,37
27,28
22,23
19,20
14,15
11,12
6,7
B
y
te 2
-
-
-
-
58,59
53,54
38,37
50,51
45,46
B
y
te 3
43,42
27,28
22,23
19,20
14,15
11,12
Reserved
Reserved
Reserved
Reserved
6,7
IDT
®
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
12
1414G—08/15/12
SMBus Table: Output Enable Readback
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
Reserved Reserved R 0
Bit 6
Reserved Reserved R 0
Bit 5
Reserved Reserved R 0
Bit 4
Reserved Reserved R 0
Bit 3
OE11# Output Control (Disable = Hi-Z) R Enabled Disabled X
Bit 2
OE10# Output Control (Disable = Hi-Z) R Enabled Disabled X
Bit 1
OE9# Output Control (Disable = Hi-Z) R Enabled Disabled X
Bit 0
OE8# Output Control (Disable = Hi-Z) R Enabled Disabled X
Note: For an output to be enabled, BOTH the Output Enable Bit and the OE# pin must be enabled.
This means that the Output Enable Bit must be '1' and the corresponding OE# pin must be '0'.
SMBus Table: Vendor & Revision ID Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RID3 R - - X
Bit 6
RID2 R - - X
Bit 5
RID1 R - - X
Bit 4
RID0 R - - X
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 1
Bit 0
VID0 R - - 0
SMBus Table: DEVICE ID
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
RW 0
Bit 6
RW 0
Bit 5
RW 0
Bit 4
RW 0
Bit 3
RW 1
Bit 2
RW 1
Bit 1
RW 0
Bit 0
RW 0
SMBus Table: Byte Count Register
Pin # Name Control Function T
yp
e0 1 PWD
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 0
Bit 2
BC2 RW - - 1
Bit 1
BC1 RW - - 1
Bit 0
BC0 RW - - 1
Reserved
Reserved
- Reserved
B
y
te 5
50,51
45,46
-
-
-
VENDOR ID
-
-
-
-
REVISION ID
-
-
-
B
y
te 6
-
-
-
-
-
-
-
-
B
y
te 7
-
Writing to this register configures how
many bytes will be read back.
-
-
-
-
-
-
-
Device ID 1
Device ID 6
Device ID 7 (MSB)
Device ID is 0C Hex
Device ID 5
Device ID 4
Device ID 3
Device ID 0
Device ID 2
Reserved
58,59
53,54
B
y
te 4
-
P1-P3P4-P6P7-P9P10-P12P13-P14

9DB1200CGLF

Mfr. #:
Buy 9DB1200CGLF
Manufacturer:
IDT
Description:
Clock Buffer 12 OUTPUT PCIE GEN2 BUFFER w/QPI
Lifecycle:
New from this manufacturer.
Delivery:
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