7009L20PFG Datasheet 7009L20PFGI, 7009L15PFG, 7009L20PFGI8 | P13-P15

6.42

IDT7009L

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing

(1,5)

Truth Table IV — Interrupt Flag

(1,4,5)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE

or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

NOTES:

1. Assumes BUSY

L = BUSYR =VIH.

2. If BUSY

L = VIL, then no change.

3. If BUSY

R = VIL, then no change.

4. INT

L and INTR must be initialized at power-up.

5. Refer to Chip Enable Truth Table.

4839 drw 15

ADDR

"A"

INTERRUPT SET ADDRESS

"A"

R/W

"A"

(3)

(4)

INS

(3)

INT

"B"

(2)

4839 drw 16

ADDR

"B"

INTERRUPT CLEAR ADDRESS

"B"

(3)

INR

(3)

INT

"B"

(2)

Left Port Right Port

FunctionR/W

16L

-A

INT

R/W

16R

-A

INT

L L X 1FFFF X X X X X L

(2)

Set Right INT

Flag

X X X X X X L L 1FFFF H

)

Reset Right INT

Flag

XXX X L

(3 )

L L X 1FFFE X Set Left INT

Flag

X L L 1FFFE H

(2)

X X X X X Reset Left INT

Flag

4839 tbl 16

IDT7009L

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT7009 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location

in memory. The IDT7009 has an automatic power down feature controlled

by CE. The CE0 and CE1 control the on-chip power down circuitry that

permits the respective port to go into a standby mode when not selected

(CE = VIH). When a port is enabled, access to the entire memory array

is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INT

L) is asserted when the right port writes to memory location 1FFFE

(HEX), where a write is defined as CER = R/WR = VIL per Truth Table

IV. The left port clears the interrupt through access of address location

1FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right

port interrupt flag (INTR) is asserted when the left port writes to memory

location 1FFFF (HEX) and to clear the interrupt flag (INTR), the right port

must read the memory location 1FFFF. The message (8 bits) at 1FFFE

or 1FFFF is user-defined since it is an addressable SRAM location. If the

interrupt function is not used, address locations 1FFFE and 1FFFF are

not used as mail boxes, but as part of the random access memory. Refer

to Table IV for the interrupt operation.

NOTES:

1. Pins BUSY

L and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7009 are

push-pull, not open drain outputs. On slaves the BUSY

input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t

APS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY

L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY

R outputs are driving LOW regardless of actual logic level on the pin.

4. Refer to Chip Enable Truth Table.

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7009.

2. There are eight semaphore flags written to via I/O

0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2.

3. CE = V

IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Truth Table V —Address BUSY

Arbitration

(4)

Truth Table VI — Example of Semaphore Procurement Sequence

(1,2,3)

Inputs Outputs

Function

-A

16L

-A

16R

BUSY

(1)

BUSY

(1 )

X X NO MATCH H H Normal

H X MATCH H H Normal

X H MATCH H H Normal

LL MATCH (2) (2)

Write

Inhibit

(3 )

4839 tbl 17

Functions D

- D

Left D

- D

Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

4839 tbl 18

6.42

IDT7009L

High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT7009 RAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

can result in a glitched internal write inhibit signal and corrupted data

in the slave.

Semaphores

The IDT7009 is an extremely fast Dual-Port 128K x 8 CMOS Static

RAM with an additional 8 address locations dedicated to binary semaphore

flags. These flags allow either processor on the left or right side of the Dual-

Port RAM to claim a privilege over the other processor for functions defined

by the system designer’s software. As an example, the semaphore can

be used by one processor to inhibit the other from accessing a portion of

the Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be read from,

or written to, at the same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

in the non-semaphore portion of the Dual-Port RAM. These devices have

an automatic power-down feature controlled by CE, the Dual-Port RAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is shown in

Truth Table II where CE and SEM are both HIGH.

Systems which can best use the IDT7009 contain multiple processors

or controllers and are typically very high-speed systems which are

software controlled or software intensive. These systems can benefit from

a performance increase offered by the IDT7009s hardware semaphores,

which provide a lockout mechanism without requiring complex program-

ming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying

configurations. The IDT7009 does not use its semaphore flags to control

any resources through hardware, thus allowing the system designer total

flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred in

either processor. This can prove to be a major advantage in very high-

speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,

from one port to the other to indicate that a shared resource is in use. The

semaphores provide a hardware assist for a use assignment method

called “Token Passing Allocation.” In this method, the state of a semaphore

latch is used as a token indicating that shared resource is in use. If the left

processor wants to use this resource, it requests the token by setting the

latch. This processor then verifies its success in setting the latch by reading

it. If it was successful, it proceeds to assume control over the shared

resource. If it was not successful in setting the latch, it determines that the

right side processor has set the latch first, has the token and is using the

shared resource. The left processor can then either repeatedly request

that semaphore’s status or remove its request for that semaphore to perform

Width Expansion Busy Logic

Master/Slave Arrays

When expanding an IDT7009 RAM array in width while using BUSY

logic, one master part is used to decide which side of the RAMs array will

receive a BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master, use

the BUSY signal as a write inhibit signal. Thus on the IDT7009 RAM the

BUSY pin is an output if the part is used as a master (M/S pin = VIH), and

the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown

in Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the

array and another master indicating BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and

inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSY flag to be output from the master before the actual

write pulse can be initiated with the R/W signal. Failure to observe this timing

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7009 RAMs.

4839 drw 17

MASTER

Dual Port RAM

BUSY

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

SLAVE

Dual Port RAM

BUSY

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

7009L20PFG

Mfr. #:

Buy 7009L20PFG

Manufacturer:

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Description:

SRAM 128K X 8 5V ASYNC DPRAM

Lifecycle:

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7009L20PFG

7009L20PFG

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