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7009L20PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
4
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Truth Table I: Chip Enable
(1,2)
Truth Table II: Non-Contention Read/Write Control
NOTES:
1. A
0L – A16L ≠ A0R – A16R.
2. Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control
(1)
NOTES:
1. There are eight semaphore flags written to via I/O
0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
NOTES:
1. Chip Enable references are shown above with the actual CE
0 and CE1 levels, CE is a reference only.
2. 'H' = V
IH and 'L' = VIL.
3. CMOS standby requires 'X' to be either
< 0.2V or > VCC - 0.2V.
CE CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
<
0.2V >V
CC
-0.2V Port Selected (CMOS Active)
H
V
IH
X Port Deselected (TTL Inactive)
XV
IL
Port Deselected (TTL Inactive)
>
V
CC
-0.2V X Port Deselected (CMOS Inactive)
X<
0.2V Port Deselected (CMOS Inactive)
4839 tbl 06
Inputs
(1 )
Outputs
Mode
CE
(2 )
R/W
OE SEM
I/O
0-7
H X X H High-Z Deselected: Power-Down
LLXHDATA
IN
Write to memory
LHLHDATA
OUT
Read memory
X X H X High-Z Outputs Disabled
4839 drw 07
Inputs Outputs
Mode
CE
(2)
R/W
OE SEM
I/O
0-7
HHLLDATA
OUT
Read Semaphore Flag Data Out
H
↑
XLDATA
IN
Write I/O
0
into Semaphore Flag
LXXL
______
Not Allowed
4839 tbl 08
6.42
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(2)
(VCC = 5.0V ± 10%)
NOTES:
1. At Vcc
< 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
Symbol Parameter Test Conditions
7009L
UnitMin. Max.
|I
LI
| Input Leakage Current
(1 )
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
5µA
|I
LO
|
Output Leakage Current
CE = V
IH
, V
OUT
= 0V to V
CC
___
5µA
V
OL
Output Low Voltage I
OL
= 4mA
___
0.4 V
V
OH
Output High Voltage I
OH
= -4mA 2.4
___
V
4839 tbl 09
NOTES:
1. V
CC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)
2. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change.
4. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(VCC = 5.0V ± 10%)
Symbol Parameter Test Condition Version
7009L15
Com'l Only
7009L20
Com'l & Ind
Unit
Typ.
(1 )
Max Typ.
(1)
Max
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(2 )
COM'L L 220 340 200 300
mA
IND L
____ ____
200 360
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
= CE
R
= V
IH
SEM
R
= SEM
L
= V
IH
f = f
MAX
(2 )
COM'L L 65 100 50 75
mA
IND L
____ ____
50 120
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(4)
Active Port Outputs Disabled,
f=f
MAX
(2 )
,
SEM
R
= SEM
L
= V
IH
COM'L L 145 225 130 195
mA
IND L
____ ____
130 235
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports CE
L
and
CE
R
> V
CC
- 0.2V, V
IN
> V
CC
- 0.2V
or V
IN
< 0.2V, f = 0
(3 )
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L L 0.2 3.0 0.2 3.0
mA
IND L
____ ____
0.2
6.0
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(4)
,
SEM
R
= SEM
L
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V,
Active Port Outputs Disabled, f = f
MAX
(2)
COM'L L 135 220 120 190
mA
IND L
____ ____
120 230
4839 tbl 10
6
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing of Power-Up Power-Down
Waveform of Read Cycles
(5)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
BDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE, tACE, tAA or tBDD.
5. SEM = V
IH.
6. Refer to Chip Enable Truth Table.
AC Test Conditions
Figure 2. Output Test Load
(for t
LZ, tHZ, tWZ, tOW)
* Including scope and jig.
Figure 1. AC Output Test Load
4839 drw 04
893Ω
30pF
347Ω
5V
DATA
OUT
BUSY
INT
893Ω
5pF*
347Ω
5V
DATA
OUT
4839 drw 03
t
RC
R/W
CE
(6)
ADDR
t
AA
OE
4839 drw 05
(4)
t
ACE
(4)
t
AOE
(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3,4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
CE
4839 drw 06
t
PU
I
CC
I
SB
t
PD
(6)
50%
50%
.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
4839 tbl 11
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

7009L20PFG

Mfr. #:
Buy 7009L20PFG
Manufacturer:
IDT
Description:
SRAM 128K X 8 5V ASYNC DPRAM
Lifecycle:
New from this manufacturer.
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