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7009L20PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
6.42
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
7
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranted by device characterization, but is not production tested.
3. To access RAM, CE= V
IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for t
DH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual t
DH will always be smaller than the actual tOW.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
7009L15
Com'l Only
7009L20
Com'l & Ind
UnitSymbol Parameter Min.Max.Min.Max.
READ CYCLE
t
RC
Read Cycle Time 15
____
20
____
ns
t
AA
Address Access Time
____
15
____
20 ns
t
ACE
Chip Enable Access Time
(4)
____
15
____
20 ns
t
AOE
Output Enable Access Time
____
10
____
12 ns
t
OH
Output Hold from Address Change 3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
3
____
3
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10 ns
t
PU
Chip Enable to Power Up Time
(2 )
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2 )
____
15
____
20 ns
t
SOP
Semaphore Flag Update Pulse (OE or SEM)10
____
10
____
ns
t
SAA
Semaphore Address Access Time
____
15
____
20 ns
4839 tbl 12
Symbol Parameter
7009L15
Com'l Only
7009L20
Com'l & Ind
UnitMin. Max. Min. Max.
WRITE CYCLE
t
WC
Write Cycle Time 15
____
20
____
ns
t
EW
Chip Enable to End-of-Write
(3 )
12
____
15
____
ns
t
AW
Address Valid to End-of-Write 12
____
15
____
ns
t
AS
Address Set-up Time
(3 )
0
____
0
____
ns
t
WP
Write Pulse Width 12
____
15
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
15
____
ns
t
HZ
Output High-Z Time
(1,2)
____
10
____
10 ns
t
DH
Data Hold Time
(4 )
0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1,2)
____
10
____
10 ns
t
OW
Output Active from End-of-Write
(1 , 2 ,4 )
0
____
0
____
ns
t
SWRD
SEM Flag Write to Read Time
5
____
5
____
ns
t
SPS
SEM Flag Contention Window
5
____
5
____
ns
4839 tbl 13
8
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
(1,5)
NOTES:
1. R/W or CE
= VIH during all address transitions.
2. A write occurs during the overlap (t
EW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.
3. t
WR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE
or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE
or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE = V
IL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t
DW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t
WP.
9. To access RAM, CE
= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
R/W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
CE or SEM
(6)
(4) (4)
(3)
4839 drw 07
(7)
(7)
(9,10)
4839 drw 08
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/W
t
AW
t
EW
(3)
(2)
(6)
CE or SEM
(9,10)
6.42
IDT7009L
High-Speed 128K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
9
Timing Waveform of Semaphore Read after Write Timing, Either Side
(1)
NOTES:
1. D
OR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W
"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If t
SPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
Timing Waveform of Semaphore Write Contention
(1,3,4)
NOTES:
1. CE = V
IH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATA
OUT VALID" represents all I/O's (I/O0 - I/O7) equal to the semaphore value.
SEM
4839 drw 09
t
AW
t
EW
DATA
0
VALID ADDRESS
t
SAA
R/W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
VALID
(2)
t
DW
t
WP
t
DH
t
AS
t
SWRD
t
AOE
t
SOP
Read Cycle
Write Cycle
A
0
-A
2
OE
t
SOP
SEM
"A"
4839 drw 10
t
SPS
MATCH
R/W
"A"
MATCH
A
0"A"
-A
2"A"
SIDE "A"
(2)
SEM
"B"
R/W
"B"
A
0"B"
-A
2"B"
SIDE
"B"
(2)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

7009L20PFG

Mfr. #:
Buy 7009L20PFG
Manufacturer:
IDT
Description:
SRAM 128K X 8 5V ASYNC DPRAM
Lifecycle:
New from this manufacturer.
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