DATASHEET
9SQL4952 REVISION D 03/25/16 1 ©2016 Integrated Device Technology, Inc.
2-output CK420BQ Derivative 9SQL4952
Description
The 9SQL4952 generates 2 100MHz CPU/SRC outputs that
exceed the requirements of the CK420BQ specification. The
device has 2 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off. It also provides a copy of the 25MHz internal XO.
The 9SQL4952 supports both Common Clock and Separate
Reference Clock architectures.
Recommended Application
2-output CK420BQ Derivative
Output Features
• 2-100MHz push-pull Low-power (LP) HCSL DIF pairs
• Integrated terminations for 85Ω Zout
• 1 - 3.3V 25MHz LVCMOS REF output
Key Specifications
• DIF outputs:
• Cycle-to-cycle jitter <50ps
• Output-to-output skew <50ps
• PCIe Gen1-2-3 compliant with SSC on or off
• QPI compliant (SSC on or off)
• SAS12G compliant (SSC off)
• 12k-20M phase jitter <2ps rms (SSC off)
• REF output:
• Phase jitter <300fs rms (SSC off) and < 1ps RMS (SSC
on)
• ±50ppm frequency accuracy on all clocks
Features/Benefits
• Direct connection to 85 transmission lines; saves 8
resistors compared to standard HCSL
• 112mW typical power consumption; eliminates thermal
concerns
• Contains default configuration; SMBus interface not
required for device operation
• OE# pins; support DIF power management
• 25MHz input frequency; standard crystal frequency
• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
• DIF outputs blocked until PLL is locked; clean system
start-up
• REF output can be configured to run in standby; eliminates
XO from board
• Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
XIN/CLKIN_25
X2
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
REF
vOE(1:0)#
SCLK_3.3
vSADR
DIF0
DIF1
2
IDT 603-25-150JA4C or
603-25-150JA4I 25MHz
SSC Capable
PLL
Control
Logic
