2-OUTPUT CK420BQ DERIVATIVE 4 REVISION D 03/25/16
9SQL4952 DATASHEET
Test Loads
Alternate Terminations
The 9SQL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
Rs
Rs
Low-Power Differential Output Test Load
2pF 2pF
5 inches
Zo=100ohm
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
Terminations
Device Zo ()Rs ()
9SQL4952 100 7.5
9SQL4952 85 None needed
REVISION D 03/25/16 5 2-OUTPUT CK420BQ DERIVATIVE
9SQL4952 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9SQL4952. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Electrical Characteristics–SMBus Parameters
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
Supply Voltage VDDxxx Applies to VDD pins. -0.5 3.9 V 1,2
Input Voltage V
IN
-0.5 V
D
D
+0.5 V 1,3
Input High Voltage, SMBus V
IHSMB
SMBus clock and data pins 3.9 V 1
Storage Temperature Ts -65 150 °C 1
Junction Temperature Tj 125 °C 1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.5V.
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
SMBus Input Low Voltage V
ILSMB
V
DDSMB
= 3.3V 0.8 V
SMBus Input High Voltage V
IHSMB
V
DDSMB
= 3.3V 2.1 3.6 V
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V
SMBus Sink Current I
PULLUP
@ V
OL
4mA
Nominal Bus Voltage V
DDSMB
2.7 3.6 V
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
SMB
SMBus operating frequency 400 kHz
1
Guaranteed by design and characterization, not 100% tested in production.
2-OUTPUT CK420BQ DERIVATIVE 6 REVISION D 03/25/16
9SQL4952 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Supply Voltage VDDxxx
Supply voltage for core, analog and single-ended
LVCMOS outputs.
3.135 3.3 3.465 V
Ambient Operating
Temperature
T
AMB
Industrial range -40 25 85 °C
Input High Voltage V
IH
Single-ended inputs, except SMBus 0.75xV
D
D
V
D
D
+0.3 V
Input Mid Voltage V
IM
Single-ended tri-level inputs ('_tri' suffix) 0.4xV
D
D
0.5 V
D
D
0.6xV
D
D
V
Input Low Voltage V
IL
Single-ended inputs, except SMBus -0.3 0.25xV
DD
V
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA
Input Frequency F
in
XTAL, or X1 input 25 MHz
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.35 1.8 ms 1,2
SS Modulation Frequency f
MOD
Allowable Frequency
(Trian
g
ular Modulation)
30 31.6 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1 3 clocks 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of single-ended control inputs 5 ns 1,2
Trise t
R
Rise time of single-ended control inputs 5 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
Input Current
Capacitance

9SQL4952BNLGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 O/P CK420BQ Lite OEM
Lifecycle:
New from this manufacturer.
Delivery:
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