2-OUTPUT CK420BQ DERIVATIVE 10 REVISION D 03/25/16
9SQL4952 DATASHEET
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Note: SMBus Read/Write Address is Latched on SADR
pin.
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
REVISION D 03/25/16 11 2-OUTPUT CK420BQ DERIVATIVE
9SQL4952 DATASHEET
SMBus Table: Output Enable Register
Byte 0 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
DIF OE1 Output Enable RW Low/Low Enabled 1
Bit 1
DIF OE0 Output Enable RW Low/Low Enabled 1
Bit 0
X
SMBus Table: SS Readback and Vhigh Control Register
Byte 1 Name Control Function Type 0 1 Default
Bit 7
SSENRB1 SS Enable Readback Bit1
R
Latch
Bit 6
SSENRB1 SS Enable Readback Bit0
R
Latch
Bit 5
SSEN_SWCNTRL Enable SW control of SS RW SS control locked
Values in B1[4:3]
control SS amount.
0
Bit 4
SSENSW1 SS Enable Software Ctl Bit1
RW
1
0
Bit 3
SSENSW0 SS Enable Software Ctl Bit0
RW
1
0
Bit 2
X
Bit 1
AMPLITUDE 1 RW 00 = 0.6V 01 = 0.7V 1
Bit 0
AMPLITUDE 0 RW 10= 0.8V 11 = 0.9V 0
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
SMBus Table: DIF Slew Rate Control Register
Byte 2 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
SLEWRATESEL DIF1 Adjust Slew Rate of DIF1 RW Slow Setting Fast Setting 1
Bit 1
SLEWRATESEL DIF0 Adjust Slew Rate of DIF0 RW Slow Setting Fast Setting 1
Bit 0
X
Note: See "Low -Power HCSL Outputs" table for slew rates.
SMBus Table: REF Control Register
Byte 3 Name Control Function Type 0 1 Default
Bit 7
RW 00 = Slowest 01 = Slow 0
Bit 6
RW 10 = Fast 11 = Faster 1
Bit 5
REF Power Down Function Wake-on-Lan Enable for REF RW
REF disabled in
Power Down
REF runs in Power
Down
0
Bit 4
REF OE REF Output Enable RW
Disabled
1
Enabled 1
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
1. The disabled state depends on Byte11[1:0]. '00' = Low, '01'=HiZ, '10'=Low, '11'=HIgh
Byte 4 is Reserved
Reserved
Reserved
Reserved
Slew Rate Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00' for SS_EN_tri = 0, '01' for SS_EN_tri
= 'M', '11 for SS_EN_tri = '1'
REF
Reserved
Controls Output Amplitude
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default).
Reserved
Reserved
Reserved
2-OUTPUT CK420BQ DERIVATIVE 12 REVISION D 03/25/16
9SQL4952 DATASHEET
SMBus Table: Revision and Vendor ID Register
Byte 5 Name Control Function Type 0 1 Default
Bit 7
RID3
R
0
Bit 6
RID2
R
0
Bit 5
RID1
R
0
Bit 4
RID0
R
1
Bit 3
VID3
R
0
Bit 2
VID2
R
0
Bit 1
VID1
R
0
Bit 0
VID0
R
1
SMBus Table: Device Type/Device ID
Byte 6 Name Control Function Type 0 1 Default
Bit 7
Device Type1
R
0
Bit 6
Device Type0
R
0
Bit 5
Device ID5
R
0
Bit 4
Device ID4
R
0
Bit 3
Device ID3
R
0
Bit 2
Device ID2
R
0
Bit 1
Device ID1
R
1
Bit 0
Device ID0
R
0
SMBus Table: Byte Count Register
Byte 7 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
BC4 RW 0
Bit 3
BC3 RW 1
Bit 2
BC2 RW 0
Bit 1
BC1 RW 0
Bit 0
BC0 RW 0
Device Type
Revision ID
Reserved
Reserved
B rev = 0001
Byte Count Programming
VENDOR ID
Reserved
0001 = IDT
00010 binary or 02 hex
9SQLxxxx=00
Writing to this register will configure how
many bytes will be read back, default is
= 8 bytes.
Device ID

9SQL4952BNLGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 O/P CK420BQ Lite OEM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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