Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. B
03/15/2013
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
IS62C25616BL, IS65C25616BL
FEATURES
• High-speed access time: 45 ns
• Low Active Power: 50 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Package: 44-pin TSOP (Type II)
• Commercial, Industrial and Automotive temper-
ature ranges available
• Lead-free available
DESCRIPTION
The ISSI IS62C25616BL and IS65C25616BL are high-
speed, 4,194,304-bit static RAMs organized as 262,144
words by 16 bits. They are fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62C25616BL and IS65C25616BL are packaged in
the JEDEC standard 44-pin TSOP (Type II).
FUNCTIONAL BLOCK DIAGRAM
MARCH 2013
A0-A17
CE
OE
WE
256K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VDD
I/O
DATA
CIRCUIT
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
256K x 16 HIGH-SPEED CMOS STATIC RAM
