IS62C25616BL-45TLI

4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/15/2013
IS62C25616BL, IS65C25616BL
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
                       -45 ns                         
Symbol Parameter  Test Conditions  Min. Max. Unit
Icc Average operating CE = VIL, Com. 10 mA
Current Vdd = Max., Ind. 10
I out= 0 mA, f = 0 Auto. 10
Icc1 Vdd Dynamic Operating Vdd = Max., CE = VIL Com. 15 mA
Supply Current Iout = 0 mA, f = fmaX Ind. 20
VIn = VIH or VIL Auto. 25
typ.
(2)
10
Isb1 TTL Standby Current Vdd = Max., Com. 1 mA
(TTL Inputs) VIn = VIH or VIL, CE VIH, Ind. 1.5
f = 0 Auto. 2
Isb2 CMOS Standby Vdd = Max., Com. 10 mA
Current (CMOS Inputs) CE Vdd – 0.2V, Ind. 15
VIn Vdd – 0.2V, Auto. 35
or VIn Vss + 0.2V, f = 0
typ.
(2)
4
Note:
1. At f = f
maX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
dd = 5V, Ta = 25
o
C and not 100% tested.
OPERATING RANGE
Range  Ambient Temperature  VDD Speed (ns)
Commercial 0°C to +70°C 5V ± 10% 45
Industrial -40°C to +85°C 5V ± 10% 45
Automotive -40°C to +125°C 5V ± 10% 45
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. B
03/15/2013
IS62C25616BL, IS65C25616BL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 
Symbol  Parameter  Min. Max. Unit
trc Read Cycle Time 45 ns
taa Address Access Time 45 ns
toHa Output Hold Time 3 ns
tace CE Access Time 45 ns
tdoe OE Access Time 20 ns
tHzoe
(2)
OE to High-Z Output 0 15 ns
tLzoe
(2)
OE to Low-Z Output 5 ns
tHzce
(2)
CE to High-Z Output 0 15 ns
tLzce
(2)
CE to Low-Z Output 5 ns
tba LB, UB Access Time 45 ns
tHzb LB, UB to High-Z Output 0 15 ns
tLzb LB, UB to Low-Z Output 0 ns
AC TEST CONDITIONS
Parameter  Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
1838
30 pF
Including
jig and
scope
994
OUTPUT
5V
1838
5 pF
Including
jig and
scope
994
OUTPUT
5V
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Figure 1
Figure 2
AC TEST LOADS
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
03/15/2013
IS62C25616BL, IS65C25616BL
READ CYCLE NO. 2
(1,3) 
(CE, OE and UB/LB Controlled)
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CE = OE = VIL, UB or LB = VIL)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB =
VIL.
3. Address is valid prior to or coincident with CE LOW transition.
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
UB_CEDR2.eps
t
HZB
ADDRESS
OE
CE
LB, UB
D
OUT
t
HZCE
t
BA
t
LZB

IS62C25616BL-45TLI

Mfr. #:
Manufacturer:
ISSI
Description:
SRAM 32M, 1.8V, 2Mx16 Async SRAM 5v
Lifecycle:
New from this manufacturer.
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