DAC8143
–11–
REV. C
ANALOG/DIGITAL DIVISION
The transfer function for the DAC8143 connect in the multiply-
ing mode as shown in Figures 16 and 17 is:
V
O
= –V
IN
A
1
2
1
+
A
2
2
2
+
A
3
2
3
+...
A
12
2
12
where A
X
assumes a value of 1 for an “ON” bit and 0 for an
“OFF” bit.
The transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 20
and is:
V
O
=
–V
IN
A
1
2
1
+
A
2
2
2
+
A
3
2
3
+ ...
A
12
2
12
The above transfer function is the division of an analog voltage
(V
REF
) by a digital word. The amplifier goes to the rails with all
bits “OFF” since division by zero is infinity. With all bits “ON”
the gain is 1 (±1 LSB). The gain becomes 4096 with the LSB,
Bit 12, “ON”.
BUFFERED DIGITAL
DATA OUT
+5V
SRO
V
REF
V
DD
R
FB
I
OUT1
DAC8143
AGND DGND
3212
15
6
14
16
1
3
2
6
V
IN
V
OUT
413
DIGITAL
INPUTS
OP-42
+
–
Figure 20. Analog/Digital Divider
APPLICATION TIPS
In most applications, linearity depends on the potential of I
OUT1,
I
OUT2,
and AGND (Pins 1, 2 and 3) being exactly equal to each
other. In most applications, the DAC is connected to an exter-
nal op amp with its noninverting input tied to ground (see Fig-
ures 16 and 17). The amplifier selected should have a low input
bias current and low drift over temperature. The amplifier’s
input offset voltage should be nulled to less than ±200 µV (less
than 10% of 1 LSB).
The operational amplifier’s noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. This resistor can
cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The V
DD
power supply should
have a low noise level with no transients greater than +17 V.
It is recommended that the digital inputs be taken to ground or
V
DD
via a high value (1 MΩ) resistor; this will prevent the accu-
mulation of static charge if the PC card is disconnected from the
system.
Peak supply current flows as the digital input pass through the
transition region (see Figure 4). The supply current decreases as
the input voltage approaches the supply rails (V
DD
or DGND),
i.e., rapidly slewing logic signals that settle very near the supply
rails will minimize supply current.
INTERFACING TO THE MC6800
As shown in Figure 21, the DAC8143 may be interfaced to the
6800 by successively executing memory WRITE instruction
while manipulating the data between WRITEs, so that each
WRITE presents the next bit.
In this example, the most significant bits are found in memory
locations 0000 and 0001. The four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. The data is taken from the
DB
7
line.
The serial data loading is triggered by STB
4
which is asserted by
a decoded memory WRITE to a memory location, R/W, and
Φ2. A WRITE to another address location transfers data from
input register to DAC register.
STB
1
DAC8143*
SRI
SRO
LD
2
LD
1
STB
3
STB
2
STB
4
CLR
74LS138
ADDRESS
DECODER
A
0
A
2
E
1
E
3
E
2
A
0
A
15
R/W
DB
0
DB
7
MC6800
16-BIT ADDRESS BUS
8-BIT DATA BUS
+5V
FROM SYSTEM RESET
*
ANALOG CIRCUITRY OMITTED FOR SIMPLICITY
φ2
Figure 21. DAC8143—MC6800 Interface
ADDRESS
DECODER
STROBE
LOAD
DAC8143
SRI
SRO
ADDRESS BUS
STROBE
LOAD
DAC8143
SRI
SRO
STROBE
LOAD
DAC8143
SRI
SRO
STROBE
LOAD
DAC8143
SRI
SRO
DB
X
mP
WR
Figure 19. Multiple DAC8143s with Three-Wire Interface
