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DAC8143FSZ

P1-P3P4-P6P7-P9P10-P12P13-P13
DAC8143
–6–
REV. C
DEFINITION OF SPECIFICATIONS
RESOLUTION
The resolution of a DAC is the number of states (2
n
) into which
the full-scale range (FSR) is divided (or resolved), where “n” is
equal to the number of bits.
SETTLING TIME
Time required for the analog output of the DAC to settle to
within 1/2 LSB of its final value for a given digital input stimu-
lus; i.e., zero to full-scale.
GAIN
Ratio of the DAC’s external operational amplifier output voltage
to the V
REF
input voltage when all digital inputs are HIGH.
FEEDTHROUGH ERROR
Error caused by capacitive coupling from V
REF
to output.
Feedthrough error limits are specified with all switches off.
OUTPUT CAPACITANCE
Capacitance from I
OUT1
to ground.
OUTPUT LEAKAGE CURRENT
Current appearing at I
OUT1
when all digital inputs are LOW, or
at I
OUT2
terminal when all inputs are HIGH.
GENERAL CIRCUIT INFORMATION
The DAC8143 is a 12-bit serial-input, buffered serial-output,
multiplying CMOS D/A converter. It has an R-2R resistor lad-
der network, a 12-bit input shift register, 12-bit DAC register,
control logic circuitry, and a buffered digital output stage.
The control logic forms an interface in which serial data is
loaded, under microprocessor control, into the input shift regis-
ter and then transferred, in parallel, to the DAC register. In
addition, buffered serial output data is present at the SRO pin
when input data is loaded into the input register. This buffered
data follows the digital input data (SRI) by 12 clock cycles and
is available for daisy-chaining additional DACs.
An asynchronous CLEAR function allows resetting the DAC
register to a zero code (0000 0000 0000) without altering data
stored in the registers.
A simplified circuit of the DAC8143 is shown in Figure 10. An
inversed R-2R ladder network consisting of silicon-chrome,
thin-film resistors, and twelve pairs of NMOS current-steering
switches. These switches steer binarily weighted currents into
either I
OUT1
or I
OUT2
. Switching current to I
OUT1
or I
OUT2
yields
a constant current in each ladder leg, regardless of digital input
code. This constant current results in a constant input resis-
tance at V
REF
equal to R (typically 11 kΩ). The V
REF
input may
be driven by any reference voltage or current, ac or dc, that is
within the limits stated in the Absolute Maximum Ratings chart.
The twelve output current-steering switches are in series with
the R-2R resistor ladder, and therefore, can introduce bit errors.
It was essential to design these switches such that the switch
“ON” resistance be binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch 1
of Figure 10 was designed with an “ON” resistance of 10 Ω,
Switch 2 for 20 Ω, etc., a constant 5 mV drop would then be
maintained across each switch.
To further ensure accuracy across the full temperature range,
permanently “ON” MOS switches were included in series with
the feedback resistor and the R-2R ladder’s terminating resistor.
The Simplified DAC Circuit, Figure 10, shows the location of
these switches. These series switches are equivalently scaled to
two times Switch 1 (MSB) and top Switch 12 (LSB) to main-
tain constant relative voltage drops with varying temperature.
During any testing of the resistor ladder or R
FEEDBACK
(such as
incoming inspection), V
DD
must be present to turn “ON” these
series switches.
V
REF
R
FEEDBACK
I
OUT2
I
OUT1
10kV10kV10kV
20kV 20kV 20kV 20kV 20kV
S
1
S
2
S
3
S
12
10kV
BIT 1 (MSB) BIT 12 (LSB)BIT 3BIT 2
DIGITAL INPUTS
(
SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH"
)
*
*
*
THESE SWITCHES
PERMANENTLY "ON"
Figure 10. Simplified DAC Circuit
DAC8143
–7–
REV. C
ESD PROTECTION
The DAC8143 digital inputs have been designed with ESD
resistance incorporated through careful layout and the inclusion
of input protection circuitry.
Figure 11 shows the input protection diodes. High voltage static
charges applied to the digital inputs are shunted to the supply
and ground rails through forward biased diodes.
These protection diodes were designed to clamp the inputs well
below dangerous levels during static discharge conditions.
V
DD
DTL/TTL/CMOS
INPUTS
Figure 11. Digital Input Protection
EQUIVALENT CIRCUIT ANALYSIS
Figures 12 and 13 show equivalent circuits for the DAC8143’s
internal DAC with all bits LOW and HIGH, respectively. The
reference current is switched to I
OUT2
when all data bits are LOW,
and to I
OUT1
when all bits are HIGH. The I
LEAKAGE
current
source is the combination of surface and junction leakages to the
substrate. The 1/4096 current source represents the constant
1-bit current drain through the ladder’s terminating resistor.
Output capacitance is dependent upon the digital input code.
This is because the capacitance of a MOS transistor changes
with applied gate voltage. This output capacitance varies be-
tween the low and high values.
R
FEEDBACK
I
OUT1
I
OUT2
R = 10kV
I
LEAKAGE
60pF
I
LEAKAGE
90pF
1/4096
R = 10kV
I
REF
V
REF
Figure 12. Equivalent Circuit (All Inputs LOW)
I
OUT2
I
LEAKAGE
60pF
R
FEEDBACK
I
OUT1
R = 10kV
I
LEAKAGE
90pF
1/4096
R = 10kV
I
REF
V
REF
Figure 13. Equivalent Circuit (All Inputs HIGH)
DYNAMIC PERFORMANCE
ANALOG OUTPUT IMPEDANCE
The output resistance, as in the case of the output capacitance,
varies with the digital input code. This resistance, looking back
into the I
OUT1
terminal, varies between 11 kΩ (the feedback
resistor alone when all digital input are LOW) and 7.5 kΩ (the
feedback resistor in parallel with approximately 30 kΩ of the
R-2R ladder network resistance when any single bit logic is
HIGH). Static accuracy and dynamic performance will be af-
fected by these variations.
The gain and phase stability of the output amplifier, board
layout, and power supply decoupling will all affect the dynamic
performance of the DAC8143. The use of a small compensation
capacitor may be required when high speed operational amplifi-
ers are used. It may be connected across the amplifier’s feed-
back resistor to provide the necessary phase compensation to
critically damp the output.
The considerations when using high speed amplifiers are:
1. Phase compensation (see Figures 16 and 17).
2. Power supply decoupling at the device socket and use of
proper grounding techniques.
OUTPUT AMPLIFIER CONSIDERATIONS
When using high speed op amps, a small feedback capacitor
(typically 5 pF–30 pF) should be used across the amplifiers to
minimize overshoot and ringing. For low speed or static
applications, ac specifications of the amplifier are not very criti-
cal. In high speed applications, slew rate, settling time, open-
loop gain and gain/phase margin specifications of the amplifier
should be selected for the desired performance. It has already
been noted that an offset can be caused by including the usual
bias current compensation resistor in the amplifier’s noninvert-
ing input terminal. This resistor should not be used. Instead, the
amplifier should have a bias current that is low over the tem-
perature range of interest.
Static accuracy is affected by the variation in the DAC’s output
resistance. This variation is best illustrated by using the circuit
of Figure 14 and the equation:
V
ERROR
= V
OS
1+
R
FB
R
O
V
OS
V
REF
RR R
ETC
R
FB
R
2
R
2
R
2
OP-77
Figure 14. Simplified Circuit
DAC8143
–8–
REV. C
Where R
O
is a function of the digital code, and:
R
O
= 10 kΩ for more than four bits of Logic 1,
R
O
= 30 kΩ for any single bit of Logic 1.
Therefore, the offset gain varies as follows:
at code 0011 1111 1111,
V
ERROR1
= V
OS
1+
10 kΩ
10 kΩ
= 2 V
OS
at code 0100 0000 0000,
V
ERROR2
= V
OS
1+
10 kΩ
30 kΩ
= 4/3 V
OS
The error difference is 2/3 V
OS
.
Since one LSB has a weight (for V
REF
= +10 V) of 2.4 mV for
the DAC8143, it is clearly important that V
OS
be minimized,
using either the amplifier’s pulling pins, an external pulling
network, or by selection of an amplifier with inherently low V
OS
.
Amplifiers with sufficiently low V
OS
include OP77, OP97, OP07,
OP27, and OP42.
INTERFACE LOGIC OPERATION
The microprocessor interface of the DAC8143 has been design-
ed with multiple STROBE and LOAD inputs to maximize inter-
facing options. Control signals decoding may be done on chip or
with the use of external decoding circuitry (see Figure 21).
Serial data is clocked into the input register and buffered output
stage with STB
1
, STB
2
, or STB
4
. The strobe inputs are active
on the rising edge. STB3 may be used with a falling edge clock
data.
WORD NWORD N –1
WORD N –2 WORD N –1 WORD N
BIT 11BIT 2 BIT 12
LSB
BIT 1
MSB
BIT 12
LSB
BIT 2BIT 1
MSB
SRI
BIT 2BIT 1
MSB
BIT 1
MSB
BIT 2
BIT 12
LSB
BIT 1
LSB
t
DS1
, t
DS2
, t
DS3
, t
DS4
SRO
t
DH1
, t
DH2
, t
DH3
, t
DH4
t
PD
t
STB1
t
STB2
t
STB3
t
STB4
t
STB1
t
STB2
t
STB3
t
STB4
* STROBE
(STB
1
, STB
2
, STB
4
)
12 12 1 2
t
LD1
t
LD2
t
SR1
1211
t
ASB
LD
1
AND LD
2
LOAD NEW 12-BIT WORD INTO
INPUT REGISTER AND SHIFT
OUT PREVIOUS WORD
LOAD INPUT REGISTER'S
DATA INTO DAC REGISTER
NOTES:
* STROBE WAVEFORM IS INVERTED IF
STB
3
IS USED TO STROBE SERIAL DATA
BITS INTO INPUT REGISTER.
** DATA IS STROBED INTO AND OUT OF
THE INPUT SHIFT REGISTER MSB FIRST.
Figure 15. Timing Diagram
Serial data output (SRO) follows the serial data input (SRI) by
12 clocked bits.
Holding any STROBE input at its selected state (i.e., STB
1
,
STB
2
or STB
4
at logic HIGH or STB
3
at logic LOW) will act to
prevent any further data input.
When a new data word has been entered into the input register,
it is transferred to the DAC register by asserting both LOAD
inputs.
The CLR input allows asynchronous resetting of the DAC regis-
ter to 0000 0000 0000. This reset does not affect data held in
the input registers. While in unipolar mode, a CLEAR will
result in the analog output going to 0 V. In bipolar mode, the
output will go to –V
REF
.
INTERFACE INPUT DESCRIPTION
STB
1
(Pin 4), STB
2
(Pin 8), STB
4
(Pin 11)—Input Register
and Buffered Output Strobe. Inputs Active on Rising
Edge. Selected to load serial data into input register and buff-
ered output stage. See Table I for details.
STB3 (Pin 10)—Input Register and Buffered Output
Strobe Input. Active on Falling Edge. Selected to load serial
data into input register and buffered output stage. See Table I
for details.
LD1 (Pin 5), LD2
(Pin 9)—Load DAC Register Inputs.
Active Low. Selected together to load contents of input register
into DAC register.
CLR (Pin 13)—Clear Input. Active Low. Asynchronous.
When LOW, 12-bit DAC register is forced to a zero code (0000
0000 0000) regardless of other interface inputs.
P1-P3P4-P6P7-P9P10-P12P13-P13

DAC8143FSZ

Mfr. #:
Buy DAC8143FSZ
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-Bit Current-Out Daisy-Chained
Lifecycle:
New from this manufacturer.
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