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SC16C852SVIET,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
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SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 19 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
Table 7. SC16C852SV internal registers
A3 A2 A1 Register Default
[1]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
General register set
[2]
0 0 0 RHR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
0 0 0 THR XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W
0 0 1 IER 00 CTS
interrupt
[3]
RTS
interrupt
[3]
Xoff
interrupt
[3]
Sleep
mode
[3]
modem status
interrupt
receive line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
R/W
0 1 0 FCR 00 RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX trigger
(MSB)
[3]
TX trigger
(LSB)
[3]
reserved XMIT FIFO
reset
RCVR FIFO
reset
FIFOs
enable
W
0 1 0 ISR 01 FIFOs
enabled
FIFOs
enabled
INT priority
bit 4
INT priority
bit 3
INT priority
bit 2
INT priority
bit 1
INT priority
bit 0
INT status R
0 1 1 LCR 00 divisor
latch
enable
set break set parity even parity parity enable stop bits word length
bit 1
word length
bit 0
R/W
1 0 0 MCR 00 clock
select
[3]
IRDA
enable
reserved loopback OP2A, INT
enable
(OP1A) RTS DTR R/W
1 0 1 LSR 60 FIFO data
error
THR and
TSR empty
THR empty break
interrupt
framing error parity error overrun error receive data
ready
R
1 0 1 EFCR 00 reserved reserved reserved reserved reserved Enable extra
feature bit-1
Enable extra
feature bit-0
Enable
TXLVLCNT/
RXLVLCNT
W
1 1 0 MSR X0 CD RI DSR CTS ∆
CD ∆RI ∆DSR ∆CTS R
1 1 1 SPR FF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Special register set
[4]
0 0 0 DLL XX bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
0 0 1 DLM XX bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
Second special register set
[5]
0 1 1 TXLVLCNT 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
1 0 0 RXLVLCNT 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 20 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1] The value shown in represents the register’s initialized HEX value; X = not applicable.
[2] Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
[3] This bit is only accessible when EFR[4] is set.
[4] Baud rate registers accessible only when LCR[7] is logic 1.
[5] Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
[6] Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
[7] First extra register set is only accessible when EFCR[2:1] = 01b.
[8] Second extra register set is only accessible when EFCR[2:1] = 10b.
[9] The SAMPR must be programmed before the LCR register is programmed.
Enhanced register set
[6]
0 1 0 EFR 00 Auto CTS Auto RTS special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
Cont-3 Tx,
Rx Control
Cont-2 Tx,
Rx Control
Cont-1 Tx,
Rx Control
Cont-0 Tx,
Rx Control
R/W
1 0 0 Xon-1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 0 1 Xon-2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
1 1 0 Xoff-1 00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 Xoff-2 00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W
First extra register set
[7]
0 1 0 TXINTLVL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 0 0 RXINTLVL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 FLWCNTH 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 1 FLWCNTL 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
Second extra register set
[8]
0 1 0 CLKPRES reserved reserved reserved reserved bit 3 bit 2 bit 1 bit 0 R/W
0 1 1 SAMPR
[9]
0x00 reserved reserved reserved reserved reserved reserved bit 1 bit 0 R/W
1 0 0 RS485TIME 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
1 1 0 AFCR2 0x00 reserved reserved RS485
RTS invert
AutoRS485
RTS
RS485
RTS/DTR
transmitter
disable
receiver
disable
9-bit enable R/W
1 1 1 AFCR1 0x00 concurrent
write
reserved reserved sleep RX
LOW
reserved RTS/CTS
mapped to
DTR/DSR
software
reset
TSR
interrupt
R/W
Table 7. SC16C852SV internal registers
…continued
A3 A2 A1 Register Default
[1]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 21 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (AD7 to AD0) to
the transmit FIFO. The THR empty flag in the LSR will be set to a logic 1 when the
transmit FIFO is empty or when data is transferred to the TSR.
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a
Receive Serial Shift Register (RSR). Receive data is removed from the SC16C852SV
receive FIFO by reading the RHR. The receive section provides a mechanism to prevent
false starts. On the falling edge of a start or false start bit, an internal receiver counter
starts counting clocks at the sampling rate. After
SAMPR
⁄
2
1
clocks, the start bit time should
be shifted to the center of the start bit. At this time the start bit is sampled, and if it is still a
logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA, INTB output pins.
1. SAMPR is the sampling rate of 16×, 8× or 4×.
Table 8. Interrupt Enable Register bits description
Bit Symbol Description
7 IER[7] CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C852SV issues an interrupt when
the
CTS pin transitions from a logic 0 to a logic 1.
6 IER[6] RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C852SV issues an interrupt when
the
RTS pin transitions from a logic 0 to a logic 1.
5 IER[5] Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the receive Xoff interrupt
4 IER[4] Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode
3 IER[3] Modem Status Interrupt. This interrupt will be issued whenever there is a modem
status change as reflected in MSR[3:0].
logic 0 = disable the modem status register interrupt (normal default condition)
logic 1 = enable the modem status register interrupt
2 IER[2] Receive Line Status interrupt. This interrupt will be issued whenever a receive
data error condition exists as reflected in LSR[4:1].
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC16C852SVIET,157

Mfr. #:
Buy SC16C852SVIET,157
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART 2-CH 128Byte FIFO 1.8V 36-Pin
Lifecycle:
New from this manufacturer.
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