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SC16C852SVIET,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 31 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.14 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bit 0 through bit 4 provide single or dual character software flow control selection. When
the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double 8-bit words
are concatenated into two sequential numbers.
[1] Enhanced function control bits: IER[7:4], ISR[5:4], FCR[5:4] and MCR[7:5].
Table 23. Enhanced Feature Register bits description
Bit Symbol Description
7 EFR[7] Automatic CTS flow control.
logic 0 = automatic CTS flow control is disabled (normal default condition)
logic 1 = enable automatic CTS flow control. Transmission will stop when
CTS
goes to a logical 1. Transmission will resume when the
CTS signal returns to a
logical 0.
6 EFR[6] Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger level and
RTS will go to a logic 1 at the next trigger level. RTS will return to a logic 0 when
data is unloaded below the next lower trigger level (programmed trigger level 1).
The state of this register bit changes with the status of the hardware flow control.
RTS functions normally when hardware flow control is disabled.
logic 0 = automatic RTS flow control is disabled (normal default condition)
logic 1 = enable automatic RTS flow control
5 EFR[5] Special Character Detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. The SC16C852SV compares each
incoming receive character with Xoff2 data. If a match exists, the received data
will be transferred to FIFO and ISR[4] will be set to indicate detection of special
character. Bit-0 in the X-registers corresponds with the LSB bit for the receive
character. When this feature is enabled, the normal software flow control must
be disabled (EFR[3:0] must be set to a logic 0).
4 EFR[4] Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4], and
MCR[7:5] can be modified and latched. After modifying any bits in the enhanced
registers, EFR[4] can be set to a logic 0 to latch the new values. This feature
prevents existing software from altering or overwriting the SC16C852SV
enhanced functions.
logic 0 = disable/latch enhanced features
[1]
logic 1 = enables the enhanced functions
[1]
. When this bit is set to a logic 1, all
enhanced features of the SC16C852SV are enabled and user settings stored
during a reset will be restored.
3:0 EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition. Combinations
of software flow control can be selected by programming these bits. See
Table 24.
Table 24. Software flow control functions
[1]
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0 0 X X No transmit flow control
1 0 X X Transmit Xon1/Xoff1
0 1 X X Transmit Xon2/Xoff2
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 32 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
[1] When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
7.15 Transmit Interrupt Level register (TXINTLVL)
This 8-bit register is used store the transmit FIFO trigger levels used for interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 25 shows trigger level register bit settings.
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.16 Receive Interrupt Level register (RXINTLVL)
This 8-bit register is used store the receive FIFO trigger levels used for interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 26 shows trigger level register bit settings.
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
1 1 X X Transmit Xon1 and Xon2/Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1/Xoff1
X X 0 1 Receiver compares Xon2/Xoff2
1011Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0111Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1111Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Table 24. Software flow control functions
[1]
…continued
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
Table 25. TXINTLVL register bits description
Bit Symbol Description
7:0 TXINTLVL[7:0] This register stores the programmable transmit interrupt trigger levels for
128-byte FIFO mode.
[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 26. RXINTLVL register bits description
Bit Symbol Description
7:0 RXINTLVL[7:0] This register stores the programmable receive interrupt trigger levels for
128-byte FIFO mode.
[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 33 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control. Table 27 shows transmission control
register bit settings; see Section 6.5.
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control. Table 28 shows transmission control
register bit settings; see Section 6.5.
[1] For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.19 Clock Prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 27. FLWCNTH register bits description
Bit Symbol Description
7:0 FLWCNTH[7:0] This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode.
[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 28. FLWCNTL register bits description
Bit Symbol Description
7:0 FLWCNTL[7:0] This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode.
[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 29. Clock Prescaler register description
Bit Symbol Description
7:4 CLKPRES[7:4] reserved
3:0 CLKPRES[3:0] clock prescaler value; reset to 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC16C852SVIET,157

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Buy SC16C852SVIET,157
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART 2-CH 128Byte FIFO 1.8V 36-Pin
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New from this manufacturer.
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