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SC16C852SVIET,157

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 25 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.4 Interrupt Status Register (ISR)
The SC16C852SV provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. A lower level interrupt may be seen after servicing the
higher level interrupt and re-reading the interrupt status bits. Table 12 “Interrupt source”
shows the data values (bits 5:0) for the six prioritized interrupt levels and the interrupt
sources associated with each of these interrupt levels.
Table 12. Interrupt source
Priority
level
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
1 0 0 0 1 1 0 LSR (Receiver Line Status Register)
2 0 0 0 1 0 0 RXRDY (Received Data Ready)
2 0 0 1 1 0 0 RXRDY (Receive Data time-out)
3 0 0 0 0 1 0 TXRDY (Transmitter Holding
Register Empty)
4 0 0 0 0 0 0 MSR (Modem Status Register)
5 0 1 0 0 0 0 RXRDY (Received Xoff signal)/
Special character
6 1 0 0 0 0 0 CTS, RTS change of state
Table 13. Interrupt Status Register bits description
Bit Symbol Description
7:6 ISR[7:6] FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852SV mode.
logic 0 or cleared = default condition
5:4 ISR[5:4] INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a logic 1,
the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1 ISR[3:1] INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see
Table 12).
logic 0 or cleared = default condition
0 ISR[0] INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 26 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 14. Line Control Register bits description
Bit Symbol Description
7 LCR[7] Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
6 LCR[6] Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
5:3 LCR[5:3] Programs the parity conditions (see
Table 15).
2 LCR[2] Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Table 16).
logic 0 or cleared = default condition
1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 17).
logic 0 or cleared = default condition
Table 15. LCR[5:3] parity selection
LCR[5] LCR[4] LCR[3] Parity selection
X X 0 no parity
X 0 1 odd parity
0 1 1 even parity
0 0 1 forced parity ‘1’
1 1 1 forced parity ‘0’
Table 16. LCR[2] stop bit length
LCR[2] Word length (bits) Stop bit length (bit times)
0 5, 6, 7, 8 1
15 1
1
⁄
2
1 6, 7, 8 2
Table 17. LCR[1:0] word length
LCR[1] LCR[0] Word length (bits)
00 5
01 6
10 7
11 8
SC16C852SV_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 23 September 2008 27 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 18. Modem Control Register bits description
Bit Symbol Description
7 MCR[7] Clock select
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6 MCR[6] IR enable (see
Figure 15).
logic 0 = enable the standard modem receive and transmit input/output interface
(normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a logic 0
during idle data conditions.
5 MCR[5] Reserved; set to ‘0’.
4 MCR[4] Loopback. Enable the local Loopback mode (diagnostics). In this mode the
transmitter output (
TX) and the receiver input (RX), CTS, DSR, CD, and RI are
disconnected from the SC16C852SV I/O pins. Internally the modem data and
control pins are connected into a loopback data configuration (see
Figure 7). In
this mode, the receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts continue to be
controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
3 MCR[3]
OP2A/OP2B, INT enable
logic 0 = forces INT (A, B) outputs to the 3-state mode (normal default condition)
logic 1 = forces the INT (A, B) outputs to the active mode
In Loopback mode, this bit is used to write the state of the modem
CD interface
signal.
2 MCR[2] This bit is used in the Loopback mode only. In the Loopback mode, this bit is used
to write the state of the modem
RI interface signal.
1 MCR[1]
RTS
logic 0 = force
RTS output to a logic 1 (normal default condition)
logic 1 = force
RTS output to a logic 0
0 MCR[0]
DTR
logic 0 = force
DTR output to a logic 1 (normal default condition)
logic 1 = force
DTR output to a logic 0
Table 19. Interrupt output control
MCR[3] INT (A, B) output
0 3-state
1 active
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

SC16C852SVIET,157

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Buy SC16C852SVIET,157
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART 2-CH 128Byte FIFO 1.8V 36-Pin
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