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Document Number: 73868
S11-0975–Rev. C, 16-May-11
Vishay Siliconix
SiP11203, SiP11204
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SYNCHRONOUS RECTIFIER PHASE-IN AND
RISING EDGE DELAY
(CONT’D)
The three modes of operation experienced during
synchronous rectifier phase-in are, in order
:
• Some number of converter switching cycles may
occur during which ΔT
DEL
≥ 2/f
CONVERTER
. During
this interval, the synchronous rectifiers are held off
for a long enough time that they will act as conven
ional diodes only. This interval of operation will be
some portion of the time it takes for the voltage on
the V
REF
pin to climb to its final 1.225 V value.
• Some number of converter switching cycles will
occur during which 2/f
CONVERTER
> ΔT
DEL
>
ΔT
DEL(FINAL)
. During this interval, the synchronous
rectifiers are held off for a portion of their possible
conduction interval, with that percentage
decreasing in a 1/x fashion from 100 % of their
possible conduction time to a percentage set by
R
DEL
and f
CONVERTER
. This interval of operation
will be the remainder of the time it takes for the
voltage on the V
REF
pin to climb to its final 1.225 V
value.
• When V
REF
is equal to 1.225 V, normal converter
operation occurs, with the synchronous rectifiers
being held off for a time T
DEL(FINAL)
. This final delay
time can be made equal to the inherent propagation
delay of the IC’s output drivers, as described below.
The synchronous rectifier phase-in is diagrammed in
Figure 7.
Connecting R
DEL
to V
L
will completely disable the
synchronous rectifier phase-in circuitry. The rectifier
MOSFETs will then transition directly from diode-mode
full synchronous rectifier operation when the IC’s V
L
supply exceeds the UVLO
R
threshold. The residual
rising-edge delay otherwise introduced by R
DEL
will
also be set to zero. (Note: By examination of the above
equations, grounding the R
DEL
pin could be another
means of setting ΔT
DEL
to zero. Doing so is not
recommended in practice as this will cause
unnecessary power dissipation in the IC: the supply
current will increase by 0.15 mA if R
DEL
is connected
to V
L
, but by 0.5 mA if this pin is shorted to ground.
Also, due to the internal circuitry of the ICs, the
propagation delay time is reduced by several
nanoseconds when the R
DEL
pin is connected to V
L
as
opposed to when it is grounded.)
In some applications it is desirable to make use of the
rectifier phase-in feature while eliminating the residual
ΔT
DEL
. To achieve this, the appropriate resistance
should be connected from the R
DEL
pin to ground, and
the R
DEL
pin should be pulled up to V
L
using a suitable
op-amp or comparator, such as the LMV321M7, once
the output voltage of the converter approaches its final
value. In such a circuit, V
CC
for the op-amp or
comparator should be obtained from V
L
of the
SiP11203/SiP11204.
The phase-in of synchronous rectification helps to
prevent disturbances in the output voltage at start-up,
which could occur due to the differential in output
voltage drop which occurs when the rectifier
MOSFETs make an abrupt transition from operation as
diodes to operation as synchronous rectifiers.
Figure 7. The SiP11203/SiP11204 gate-drive output signals are delayed during phase-in prevent disturbing the output voltage
time
IN
B
OUT
B
IN
A
OUT
A
Rising edge delay reduces during phase-in. Phase-in
period set R
DEL
IN
B
OUT
B
IN
A
OUT
A
Rising edge delay during normal operation. Period set
by R
DEL
(Note: can be set to zero)
Phase-In finished
Phase-In period
